Datasheet

95
ATmega323(L)
1457E11/01
Bit 3 - TXEN: Transmitter Enable
Setting this bit to one enables the USART transmitter. The transmitter will override nor-
mal port operation for the TxD pin when enabled. The disabling of the transmitter
(setting the TXEN to zero) will not become effective until ongoing and pending transmis-
sions are completed, i.e. when the transmit shift register and transmit buffer register
does not contain data to be transmitted. When disabled the transmitter will no longer
override the TxD port.
Bit 2 - UCSZ2: Character Size
The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits
(character size) in a frame the receiver and transmitter use.
Bit 1 - RXB8: Receive Data Bit 8
RXB8 is the 9th data bit of the received character when operating with serial frames with
9 data bits. Must be read before reading the low bits from UDR.
Bit 0 - TXB8: Transmit Data Bit 8
TXB8 is the 9th data bit in the character to be transmitted when operating with serial
frames with 9 data bits. Must be written before writing the low bits to UDR.
USART Control and Status
Register C UCSRC
The UCSRC register shares the same I/O location as the UBRRH register. See the
Accessing UBRRH/UCSRC Registers on page 91 section which describes how to
access this register.
Bit 7 - URSEL: Register Select
This bit selects between accessing the UCSRC or the UBRRH register. It is read as one
when reading UCSRC. The URSEL must be one when writing the UCSRC.
Bit 6 - UMSEL: USART Mode Select
This bit selects between asynchronous and synchronous mode of operation.
Bit 5:4 - UPM1:0: Parity Mode
This bit enable and set type of parity generation and check. If enabled, the transmitter
will automatically generate and send the parity of the transmitted data bits within each
frame. The receiver will generate a parity value for the incoming data and compare it to
the UPM0 setting. If a mismatch is detected, the PE flag in UCSRA will be set.
Bit 76543210
$20 ($40)
URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL UCSRC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value10000110
Table 32. USART Mode
UMSEL Mode
0 Asynchronous Operation
1 Synchronous Operation