Datasheet

9
ATmega323(L)
1457E–11/01
Figure 5. The ATmega323 AVR Enhanced RISC Architecture
The AVR uses a Harvard architecture concept
– with separate memories and buses for
program and data. The program memory is executed with a single level pipelining. While
one instruction is being executed, the next instruction is pre-fetched from the program
memory. This concept enables instructions to be executed in every clock cycle. The pro-
gram memory is In-System Reprogrammable Flash memory.
With the jump and call instructions, the whole 16K address space is directly accessed.
Most AVR instructions have a single 16-bit word format. Every program memory
address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot program section (512
to 4K bytes, see page 172) and the Application Program section. Both sections have
dedicated Lock Bits for write and read/write protection. The SPM instruction that writes
into the Application Flash memory section is allowed only in the Boot program section.
During interrupts and subroutine calls, the return address program counter (PC) is
stored on the stack. The stack is effectively allocated in the general data SRAM, and
consequently the stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The 12-bit stack pointer SP is read/write accessible in the
I/O space.
16K X 16
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
Interrupt
Unit
SPI
Unit
Watchdog
Timer
A/D Converter
MUX and Gain
Analog
Comparator
32
I/O Lines
1K x 8
EEPROM
Data Bus 8-bit
Serial
I
2
C Bus
16-bit
Timer/Counter
with PWM
8-bit
Timer/Counter
with PWM
2K x 8
Data
SRAM
Direct Addressing
Indirect Addressing
8-bit
Timer/Counter
with PWM
Serial
USART