Datasheet
71
ATmega323(L)
1457E–11/01
• Bit 4 - MSTR: Master/Slave Select
This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared
(zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be
cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-
enable SPI master mode.
• Bit 3 - CPOL: Clock Polarity
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is
low when idle. Refer to Figure 43 and Figure 44 for additional information.
• Bit 2 - CPHA: Clock Phase
Refer to Figure 43 and Figure 44 for the functionality of this bit.
• Bits 1,0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a master. SPR1 and
SPR0 have no effect on the slave. The relationship between SCK and the Oscillator
Clock frequency f
ck
is shown in Table 27.
The SPI Status Register –
SPSR
• Bit 7 - SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is gener-
ated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS
is an input and
is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alter-
natively, the SPIF bit is cleared by first reading the SPI status register with SPIF set
(one), then accessing the SPI Data Register (SPDR).
• Bit 6 - WCOL: Write COLlision flag
The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register
with WCOL set (one), and then accessing the SPI Data Register.
• Bit 5..1 - Res: Reserved Bits
These bits are reserved bits in the ATmega323 and will always read as zero.
Table 27. Relationship Between SCK and the Oscillator Frequency
SPI2X SPR1 SPR0 SCK Frequency
00 0 f
ck
/4
00 1 f
ck
/16
01 0 f
ck
/64
01 1 f
ck
/128
10 0 f
ck
/2
10 1 f
ck
/8
11 0 f
ck
/32
11 1 f
ck
/64
Bit 76543210
$0E ($2E)
SPIFWCOL-----SPI2XSPSR
Read/WriteRRRRRRRR/W
Initial Value00000000