Datasheet

ATmega323(L)

1457E–11/01

Serial Peripheral

Interface – SPI

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer

between the ATmega323 and peripheral devices or between several AVR devices. The

ATmega323 SPI includes the following features:

•

Full-duplex, 3-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

Figure 41. SPI Block Diagram

The interconnection between master and slave CPUs with SPI is shown in Figure 42.

The PB7(SCK) pin is the clock output in the Master mode and the clock input in the

Slave mode. Writing to the SPI Data Register of the master CPU starts the SPI clock

generator, and the data written shifts out of the PB5(MOSI) pin and into the PB5(MOSI)

pin of the slave CPU. After shifting one byte, the SPI clock generator stops, setting the

end of transmission flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR regis-

ter is set, an interrupt is requested. The Slave Select input, PB4(SS

), is set low to select

an individual slave SPI device. The two shift registers in the Master and the Slave can

be considered as one distributed 16-bit circular shift register. This is shown in Figure 42.

When data is shifted from the master to the slave, data is also shifted in the opposite

direction, simultaneously. During one shift cycle, data in the master and the slave is

interchanged.

SPI2X

DIVIDER

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