Datasheet

ATmega323(L)

1457E–11/01

Figure 38. Effects of Unsynchronized OCR1 Latching.

Figure 39. Effects of Unsynchronized OCR1 Latching in Overflow Mode

During the time between the write and the latch operation, a read from OCR1A or

OCR1B will read the contents of the temporary location. This means that the most

recently written value always will read out of OCR1A/B.

When the OCR1X contains $0000 or TOP, and the up/down PWM mode is selected, the

output OC1A/OC1B is updated to low or high on the next compare match according to

the settings of COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in Table 23. In

overflow PWM mode, the output OC1A/OC1B is held low or high only when the Output

Compare Register contains TOP.

PWM Output OC1x

Unsynchronized OC1x Latch

Synchronized OC1x Latch

Note: x = A or B

PWM Output OC1x

Unsynchronized OC1x Latch

Synchronized OC1x Latch

Note: X = A or B