Datasheet

ATmega323(L)

1457E–11/01

As shown in Table 20, the PWM operates at either 8, 9, or 10 bits resolution. Note the

unused bits in OCR1A, OCR1B, and TCNT1 will automatically be written to zero by

hardware. I.e. bit 9 to 15 will be set to zero in OCR1A, OCR1B, and TCNT1 if the 9-bit

PWM resolution is selected. This makes it possible for the user to perform read-modify-

write operations in any of the three resolution modes and the unused bits will be treated

as don’t care.

Note: X = A or B

Note that in the PWM mode, the 8, 9, or 10 least significant OCR1A/OCR1B bits

(depending on resolution), when written, are transferred to a temporary location. They

are latched when Timer/Counter1 reaches the value TOP. This prevents the occurrence

of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A/OCR1B

write. See Figure 38 and Figure 39 for an example in each mode.

Table 21. Timer TOP Values and PWM Frequency

PWM Resolution Timer TOP Value Frequency

8-bit $00FF (255) f

TC1

/510

9-bit $01FF (511) f

TC1

/1022

10-bit $03FF(1023) f

TC1

/2046

Table 22. Compare1 Mode Select in PWM Mode

CTC1 COM1X1 COM1X0 Effect on OCX1

0 0 0 Not connected

00 1Reserved

0 1 0 Cleared on compare match, up-counting. Set on

compare match, down-counting (non-inverted PWM).

0 1 1 Cleared on compare match, down-counting. Set on

compare match, up-counting (inverted PWM).

1 0 0 Not connected

10 1Reserved

1 1 0 Cleared on compare match, set on overflow.

1 1 1 Set on compare match, cleared on overflow.