Datasheet

50
ATmega323(L)
1457E–11/01
Figure 34. Effects of Unsynchronized OCR Latching in Up/Down Mode
Figure 35. Effects of Unsynchronized OCR Latching in Overflow Mode
Note: n = 0 or 2 (Figure 34 and Figure 35)
During the time between the write and the latch operation, a read from the Output Com-
pare Registers will read the contents of the temporary location. This means that the
most recently written value always will read out of OCR0 and OCR2.
When the Output Compare Register contains $00 or $FF, and the up/down PWM mode
is selected, the output PB3(OC0/PWM0)/PD7(OC2/PWM2) is updated to low or high on
the next compare match according to the settings of COMn1/COMn0. This is shown in
Table 16. In overflow PWM mode, the output PB3(OC0/PWM0)/PD7(OC2/PWM2) is
held low or high only when the Output Compare Register contains $FF.
PWM Output OCn
PWM Output OCn
Unsynchronized OCn Latch
Synchronized OCn Latch
Compare Value changes
Counter Value
Compare Value
Glitch
Counter Value
Compare Value
Compare Value changes
PWM Output OCn
PWM Output OCn
Unsynchronized OCn Latch
Synchronized OCn Latch
Counter Value
Compare Value
Counter Value
Compare Value
Compare Value changes
Compare Value changes
Glitch