Datasheet

35
ATmega323(L)
1457E–11/01
• Bit 4 - OCIE1A: Timer/Counter1 Output CompareA Match Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt is
executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is
set in the Timer/Counter Interrupt Flag Register
– TIFR.
• Bit 3 - OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt is
executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is
set in the Timer/Counter Interrupt Flag Register
– TIFR.
• Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt is executed if
an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the
Timer/Counter Interrupt Flag Register
– TIFR.
• Bit 1 - OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable
When the OCIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is
executed if a Compare0 match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set
in the Timer/Counter Interrupt Flag Register
– TIFR.
• Bit 0 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if
an overflow in Timer/Counter0 occurs, i.e. when the TOV0 bit is set in the Timer/Counter
Interrupt Flag Register
– TIFR.
The Timer/Counter Interrupt
Flag Register – TIFR
• Bit 7 - OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2
and the data in OCR2
– Output Compare Register2. OCF2 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by
writing a logic one to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2
Compare match Interrupt Enable), and the OCF2 are set (one), the Timer/Counter2
Compare match Interrupt is executed.
• Bit 6 - TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE2
(Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the
Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when
Timer/Counter2 changes counting direction at $00.
Bit 76543210
$38 ($58)
OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 TIFR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000