Datasheet

28
ATmega323(L)
1457E–11/01
Table 6 shows the start-up times from reset. When the CPU wakes up from power-down
or power-save, only the clock counting part of the start-up time is used. The Watchdog
oscillator is used for timing the real-time part of the start-up time. The number WDT
oscillator cycles used for each time-out is shown in Table 7.
The frequency of the Watchdog oscillator is voltage dependent as shown in the Electri-
cal Characteristics section. The device is shipped with CKSEL = “0010” (Internal RC
Oscillator, slowly rising power).
Note: 1. The BODLEVEL fuse can be used to select start-up times even if the Brown-out
Detection is disabled (BODEN fuse unprogrammed).
Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-
tion level is defined in Table 5. The POR is activated whenever V
CC
is below the
detection level. The POR circuit can be used to trigger the start-up reset, as well as to
detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from power-on. Reach-
ing the Power-on Reset threshold voltage invokes a delay counter, which determines
the delay, for which the device is kept in RESET after V
CC
rise. The time-out period of
the delay counter can be defined by the user through the CKSEL fuses. The different
selections for the delay period are presented in Table 6. The RESET signal is activated
again, without any delay, when the V
CC
decreases below detection level.
Figure 25. MCU Start-up, RESET
Tied to VCC
Table 7. Number of Watchdog Oscillator Cycles
BODLEVEL
(1)
V
CC
Condition Time-out Number of Cycles
Unprogrammed 2.7V 30 µs 8
Unprogrammed 2.7V 130 µs 32
Unprogrammed 2.7V 4.2 ms 1K
Unprogrammed 2.7V 67 ms 16K
Programmed 4.0V 10 µs 8
Programmed 4.0V 35 µs 32
Programmed 4.0V 5.8 ms 4K
Programmed 4.0V 92 ms 64K
VCC
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST