Datasheet

210
ATmega323(L)
1457E–11/01
2-wire Serial Interface Characteristics
Table 74 describes the requirements for devices connected to the 2-wire Serial Bus. The ATmega323 2-wire Serial Inter-
face meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 107.
Notes: 1. In ATmega323, this parameter is characterized and not 100% tested.
2. Required only for f
SCL
> 100 kHz.
3. C
b
= capacitance of one bus line in pF.
4. f
CK
= CPU clock frequency
5. This requirement applies to all ATmega323 2-wire Serial Interface operation. Other devices connected to the 2-wire Serial
Bus need only obey the general f
SCL
requirement.
6. The actual low period generated by the ATmega323 2-wire Serial Interface is (1/f
SCL
- 2/f
CK
), thus f
CK
must be greater than 6
MHz for the low time requirement to be strictly met at f
SCL
= 100 kHz.
7. The actual low period generated by the ATmega323 2-wire Serial Interface is (1/f
SCL
- 2/f
CK
), thus the low time requirement
will not be strictly met for f
SCL
> 308 kHz when f
CK
= 8 MHz. Still, ATmega323 devices connected to the bus may communi-
Table 74. 2-wire Serial Bus Requirements
Symbol Parameter Condition Min Max Units
VIL
Input Low-voltage -0.5 0.3 V
CC
V
VIH
Input High-voltage 0.7 V
CC
V
CC
+ 0.5 V
Vhys
(1)
Hysteresis of Schmitt Trigger Inputs 0.05 V
CC
(2)
-V
VOL
(1)
Output Low-voltage 3 mA sink current 0 0.4 V
tof
(1)
Output Fall Time from V
IHmin
to V
ILmax
10 pF < C
b
< 400 pF
(3)
20 + 0.1C
b
(3)(2)
250 ns
tSP
(1)
Spikes Suppressed by Input Filter 0 50
(2)
ns
I
i
Input Current each I/O Pin 0.1V
CC
< V
i
< 0.9V
CC
-10 10 µA
C
i
(1)
Capacitance for each I/O Pin - 10 pF
f
SCL
SCL Clock Frequency f
CK
(4)
> max(16f
SCL
, 250kHz)
(5)
0400kHz
t
HD;STA
Hold Time (repeated) START Condition
f
SCL
≤ 100 kHz 4.0 - µs
f
SCL
> 100 kHz 0.6 - µs
t
LOW
Low Period of the SCL Clock
f
SCL
≤ 100 kHz
(6)
4.7 - µs
f
SCL
> 100 kHz
(7)
1.3 - µs
t
HIGH
High period of the SCL clock
f
SCL
≤ 100 kHz 4.0 - µs
f
SCL
> 100 kHz 0.6 - µs
t
SU;STA
Set-up time for a repeated START condition
f
SCL
≤ 100 kHz 4.7 - µs
f
SCL
> 100 kHz 0.6 - µs
t
HD;DAT
Data hold time
f
SCL
≤ 100 kHz 0 3.45 µs
f
SCL
> 100 kHz 0 0.9 µs
t
SU;DAT
Data setup time
f
SCL
≤ 100 kHz 250 - ns
f
SCL
> 100 kHz 100 - ns
t
SU;STO
Setup time for STOP condition
f
SCL
≤ 100 kHz 4.0 - µs
f
SCL
> 100 kHz 0.6 - µs
t
BUF
Bus free time between a STOP and START
condition
f
SCL
≤ 100 kHz 4.7 - µs
f
SCL
> 100 kHz 1.3 - µs