Datasheet

203
ATmega323(L)
1457E–11/01
Virtual Flash Page Read
Register
The Virtual Flash Page Read register is a virtual scan chain with length equal to the
number of bits in one Flash page plus 8, 1032 in total. Internally the shift register is 8 bit,
and the data are automatically transferred from the Flash data page byte by byte. The
first 8 cycles are used to transfer the first byte to the internal shift register, and the bits
that are shifted out during these 8 cycles should be ignored. Following this initialization,
data are shifted out starting with the LSB of the instruction with page address 0 and end-
ing with the MSB of the instruction with page address 3F. This provides an efficient way
to read one full Flash page to verify programming.
Figure 105. Virtual Flash Page Read Register
Programming algorithm All references below of type “1a”, “1b”, and so on, refer to Table 71.
Entering programming mode 1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset register.
2. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Pro-
gramming Enable register.
Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS.
2. Disable all programming instructions by usning no operation instruction 11a.
3. Enter instruction PROG_ENABLE and shift 0000_0000_0000_0000 in the pro-
gramming Enable register.
4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset register.
If PROG_ENABLE instruction is not followed by the AVR_RESET instruction, the follow-
ing algorithm should be used:
1. Enter JTAG instruction PROG_COMMANDS.
2. Disable all programming instructions by using no operation instruction 11a.
3. Enter instruction PROG_ENABLE and shift 0000_0000_0000_0000 in the Pro-
gramming Enable register.
4. Enter instruction PROG_ENABLE and shift 0000_0000_0000_0000 in the Pro-
gramming Enable register.
5. Wait until the selected oscillator has started before applying more commands.
TDI
TDO
D
A
T
A
Flash
EEPROM
Fuses
Lock Bits
STROBES
ADDRESS
State
machine