Datasheet

202
ATmega323(L)
1457E–11/01
Virtual Flash Page
Load Register
The Virtual Flash Page Load register is a virtual scan chain with length equal to the
number of bits in one Flash page, 1024. Internally the shift register is 8 bit, and the data
are automatically transferred to the Flash page buffer byte by byte. Shift in all instruction
words in the page, starting with the LSB of the instruction with page address 0 and end-
ing with the MSB of the instruction with page address 3F. This provides an efficient way
to load the entire Flash page buffer before executing Page Write.
Figure 104. Virtual Flash Page Load Register
TDI
TDO
D
A
T
A
Flash
EEPROM
Fuses
Lock Bits
STROBES
ADDRESS
State
machine