Datasheet

197
ATmega323(L)
1457E–11/01
is not used to transfer data from the shift register. The data are automatically transferred
to the Flash page buffer byte by byte in the Shift-DR state by an internal state machine.
This is the only active state:
• Shift-DR: Flash page data are shifted in from TDI by the TCK input, and
automatically loaded into the Flash page one byte at a time.
PROG_PAGEREAD ($7) The AVR specific public JTAG instruction to read one full Flash data page via the JTAG
port. The 1032 bit Virtual Flash Page Read register is selected as data register. This is a
virtual scan chain with length equal to the number of bits in one Flash page plus 8. Inter-
nally the shift register is 8 bit. Unlike most JTAG instructions, the Capture-DR state is
not used to transfer data to the shift register. The data are automatically transferred from
the Flash page buffer byte by byte in the Shift-DR state by an internal state machine.
This is the only active state:
• Shift-DR: Flash data are automatically read one byte at a time and shifted out on
TDO by the TCK input. The TDI input is ignored.
Data Registers The data registers are selected by the JTAG instruction registers described in section
“Programming specific JTAG instructions” on page 196. The data registers relevant for
programming operations are:
• Reset Register
• Programming Enable Register
• Programming Command Register
• Virtual Flash Page Load Register
• Virtual Flash Page Read Register
Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It
is required to reset the part before entering programming mode.
A high value in the Reset Register corresponds to pulling the external Reset low. The
part is reset as long as there is a high value present in the Reset Register. Depending
on the Fuse settings for the clock options, the part will remain reset for a Reset Time-
Out Period (refer to Table 6 on page 27) after releasing the Reset Register. The output
from this Data Register is not latched, so the reset will take place immediately, as shown
in Figure 93 on page 183.
Programming Enable
Register
The Programming Enable register is a 16 bit register. The contents of this register is
compared to the programming enable signature, binary code 1010_0011_0111_0000.
When the contents of the register is equal to the programming enable signature, pro-
gramming via the JTAG port is enabled. The register is reset to 0 on Power-on Reset,
and should always be reset when leaving programming mode.