Datasheet

190
ATmega323(L)
1457E–11/01
Parallel Programming
Characteristics
Figure 97. Parallel Programming Timing
Notes: 1. t
WLRH
is valid for the Write EEPROM, Write Fuse Bits and Write Lock Bits
commands.
2. tWLRH_CE is valid for the Chip Erase command.
3. tWLRH_FLASH is valid for the Write Flash command.
Table 67. Parallel Programming Characteristics, T
A
= 25°C ± 10%, V
CC
= 5 V ± 10%
Symbol Parameter Min Typ Max Units
V
PP
Programming Enable Voltage 11.5 12.5 V
I
PP
Programming Enable Current 250 µA
t
DVXH
Data and Control Valid before XTAL1 High 67 ns
t
XHXL
XTAL1 Pulse Width High 67 ns
t
XLDX
Data and Control Hold after XTAL1 Low 67 ns
t
XLWL
XTAL1 Low to WR Low 67 ns
t
BVPH
BS1 Valid before PAGEL High 67 ns
t
PHPL
PAGEL Pulse Width High 67 ns
t
PLBX
BS1 Hold after PAGEL Low 67 ns
t
PLWL
PAGEL Low to WR Low 67 ns
t
BVWL
BS1 Valid to WR Low 67 ns
t
RHBX
BS1 Hold after RDY/BSY High 67 ns
t
WLWH
WR Pulse Width Low 67 ns
t
WLRL
WR Low to RDY/BSY Low 0 2.5 µs
t
WLRH
(1)
WR Low to RDY/BSY High
(1)
11.51.9ms
t
WLRH_CE
(2)
WR Low to RDY/BSY High for Chip Erase
(2)
16 23 30 ms
t
WLRH_FLASH
(3)
WR Low to RDY/BSY High for Write Flash
(3)
81215ms
t
XLOL
XTAL1 Low to OE Low 67 ns
t
OLDV
OE Low to DATA Valid 20 ns
t
OHDZ
OE High to DATA Tri-stated 20 ns
Data & Contol
(DATA, XA0/1, BS1, BS2)
DATA
Write
Read
XTAL1
t
XHXL
t
WLWH
t
DVXH
t
XLOL
t
OLDV
t
XLDX
t
PLWL
t
WLRH
WR
RDY/BSY
OE
PAGEL
t
PHPL
t
PLBX
t
BVPH
t
XLWL
t
RHBX
t
OHDZ
t
BVWL
WLRL