Datasheet

ATmega323(L)

1457E–11/01

Figure 22 shows the internal timing concept for the register file. In a single clock cycle

an ALU operation using two register operands is executed, and the result is stored back

to the destination register.

Figure 22. Single Cycle ALU Operation

The internal data SRAM access is performed in two System Clock cycles as described

in Figure 23.

Figure 23. On-chip Data SRAM Access Cycles

I/O Memory The I/O space definition of the ATmega323 is shown in Table 2.

System Clock Ø

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

System Clock Ø

Data

Address

T1 T2 T3 T4

Prev. Address

Read

Write

Table 2. ATmega323 I/O Space

I/O Address (SRAM

Address) Name Function

$3F ($5F) SREG Status Register

$3E ($5E) SPH Stack Pointer High

$3D ($5D) SPL Stack Pointer Low

$3C ($3C) OCR0 Timer/Counter0 Output Compare Register

$3B ($5B) GICR General Interrupt Control Register

$3A ($5A) GIFR General Interrupt Flag Register

$39 ($59) TIMSK Timer/Counter Interrupt Mask Register

$38 ($58) TIFR Timer/Counter Interrupt Flag Register

$37 ($57) SPMCR SPM Control Register