Datasheet

175
ATmega323(L)
1457E–11/01
Perform a Page Write To execute page write, set up the address in the Z pointer, write “00101” to the five LSB
in SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in
R1 and R0 is ignored. The page address must be written to Z14:Z7. During this opera-
tion, Z6:Z0 must be zero to ensure that the page is written correctly. It is recommended
that the interrupts are disabled during the page write operation.
Consideration while Updating
the Boot Loader Section
Special care must be taken if the user allows the Boot Loader section to be updated by
leaving Boot Lock Bit 11 unprogrammed. An accidental write to the Boot Loader itself
can corrupt the entire Boot Loader, and further software updates might be impossible. If
it is not necessary to change the Boot Loader software itself, it is recommended to pro-
gram the Boot Lock Bit 11 to protect the Boot Loader software from any internal
software changes.
Wait for SPM Instruction to
Complete
Though the CPU is halted during page write, page erase or Lock bit write, for future
compatibility, the user software must poll for SPM complete by reading the SPMCR reg-
ister and loop until the SPMEN bit is cleared after a programming operation. See
“Assembly code example for a Boot Loader” on page 179 for a code example.
Instruction Word Read after
Page Erase, Page Write, and
Lock-bit Write
To ensure proper instruction pipelining after programming action (page erase, page
write, or lock-bit write), the SPM instruction must be followed with the sequence (.dw
$FFFF - NOP) as shown below:
spm
.dw $FFFF
nop
If not, the instruction following SPM might fail. It is not necessary to add this sequence
when the SPM instruction only loads the temporary buffer.
Avoid Reading the Application
Section During Self-
programming
During self-programming (either page erase or page write), the user software should not
read the application section. The user software itself must prevent addressing this sec-
tion during the self-programming operations. This implies that interrupts must be
disabled or moved to the Boot Loader section. Before addressing the application section
after the programming is completed, for future compatibility, the user software must
write”10001” to the five LSB in SPMCR and execute SPM within four clock cycles. Then
the user software should verify that the ASB bit is cleared. See “Assembly code exam-
ple for a Boot Loader” on page 179 for an example. Though the ASB and ASRE bits
have no special function in this device, it is important for future code compatibility that
they are treated as described above.
Boot Loader Lock-bits ATmega323 has two separate sets of Boot Lock Bits which can be set independently.
This gives the user a unique flexibility to select different levels of protection.
The user can select:
• To protect the entire Flash from a software update by the MCU
• To only protect the Boot Loader Flash section from a software update by the MCU
• To only protect application Flash section from a software update by the MCU
• Allowing software update in the entire Flash
See Table 61 for further details. The Boot Lock bits can be set in software and in Serial
or Parallel Programming mode, but they can only be cleared by a chip erase command.