Datasheet

17
ATmega323(L)
1457E–11/01
Program execution continues at address contained by the Z-register (i.e., the PC is
loaded with the contents of the Z-register).
Relative Program Addressing,
RJMP and RCALL
Figure 20. Relative Program Memory Addressing
Program execution continues at address PC + k + 1. The relative address k is from –
2048 to 2047.
The EEPROM Data
Memory
The ATmega323 contains 1K bytes of data EEPROM memory. It is organized as a sep-
arate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described on page 65 specifying the EEPROM Address Registers, the
EEPROM Data Register, and the EEPROM Control Register.
For SPI data downloading of the EEPROM, see page 191 for a detailed description.
Memory Access Times
and Instruction
Execution Timing
This section describes the general access timing concepts for instruction execution and
internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the selected
clock source for the chip. No internal clock division is used.
Figure 21 shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access register file concept. This is the basic pipe-
lining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks, and functions per power-unit.
Figure 21. The Parallel Instruction Fetches and Instruction Executions
$3FFF
1
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4