Datasheet

154
ATmega323(L)
1457E–11/01
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST - Test ReSeT - which
is not provided.
When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins,
and the TAP controller is in reset. When programmed, the input TAP signals are inter-
nally pulled high and the JTAG is enabled for Boundary-Scan and programming. The
device is shipped with this fuse programmed.
For the On-Chip Debug system, in addition the RESET
pin is monitored by the debugger
to be able to detect external reset sources. The debugger can also pull the RESET
pin
low to reset the whole system, assuming only open collectors on reset line are used in
the application.
Figure 85. Block Diagram
TAP
CONTROLLER
TDI
TDO
TCK
TMS
FLASH
MEMORY
AVR CPU
DIGITAL
PERIPHERAL
UNITS
JTAG / AVR CORE
COMMUNICATION
INTERFACE
BREAKPOINT
UNIT
FLOW CONTROL
UNIT
OCD STATUS
AND CONTROL
INTERNAL
SCAN
CHAIN
M
U
X
INSTRUCTION
REGISTER
ID
REGISTER
BYPASS
REGISTER
JTAG PROGRAMMING
INTERFACE
PC
Instruction
Address
Data
BREAKPOINT
SCAN CHAIN
ADDRESS
DECODER
ANALOG
PERIPHERIAL
UNITS
PORT A
PORT B
BOUNDARY SCAN CHAIN
Analog inputs
Control & Clock lines
DEVICE BOUNDARY