Datasheet

153
ATmega323(L)
1457E–11/01
JTAG Interface and
the On-chip Debug
System
Features: • JTAG (IEEE std. 1149.1 Compliant) Interface
• Boundary-scan Capabilities According to the JTAG Standard
• Debugger Access to:
– All Internal Peripheral Units
– Internal and External RAM
– The Internal Register File
– Program Counter
– EEPROM and Flash Memories
• Extensive On-chip Debug Support for Break Conditions, Including
– Break on Change of Program Memory Flow
– Single Step Break
– Program Memory Breakpoints on Single Address or Address Range
– Data Memory Breakpoints on Single Address or Address Range
• Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• On-chip Debugging Supported by AVR Studio
Overview The AVR IEEE std. 1149.1 compliant JTAG interface can be used for
• Testing PCBs by using the JTAG Boundary-scan Capability
• Programming the Non-volatile Memories, Fuses and Lock-bits
• On-chip Debugging
A brief description is given in the following sections. Detailed descriptions for Program-
ming via the JTAG interface, and using the Boundary-Scan Chain can be found in the
sections “Programming via the JTAG interface” on page 196 and “IEEE 1149.1 (JTAG)
Boundary-scan” on page 159, respectively. The On-Chip Debug support is considered
being private JTAG instructions, and distributed within ATMEL and to selected 3rd party
vendors only.
Figure 85 shows a block diagram of the JTAG interface and the On-Chip Debug system.
The TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP
Controller selects either the JTAG Instruction Register or one of several Data Registers
as the scan chain (shift register) between the TDI - input and TDO - output. The Instruc-
tion Register holds JTAG instructions controlling the behavior of a Data Register.
Of the Data Registers, the ID-Register, Bypass Register, and the Boundary-Scan Chain
are used for board-level testing. The JTAG Programming Interface (actually consisting
of several physical and virtual Data Registers) is used for serial programming via the
JTAG interface. The Internal Scan Chain and Break-Point Scan Chain are used for On-
Chip debugging only.
The Test Access Port –
TAP
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology,
these pins constitute the Test Access Port - TAP. These pins are
• TMS: Test mode select. This pin is used for navigating through the TAP-controller
state machine.
• TCK: Test clock. JTAG operation is synchronous to TCK
• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data
Register (Scan Chains)
• TDO: Test Data Out. Serial output data from Instruction register or Data Register