Datasheet

141
ATmega323(L)
1457E–11/01
Figure 72. Port B Schematic Diagram (Pin PB5)
Figure 73. Port B Schematic Diagram (Pin PB6)
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PB5
R
R
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR:
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
DDB5
PORTB5
SPE
MSTR
SPI MASTER
OUT
SPI SLAVE
IN
RL
RP
PUD
PUD: PULL-UP DISABLE
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PB6
R
R
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
DDB6
PORTB6
SPE
MSTR
SPI SLAVE
OUT
SPI MASTER
IN
RL
RP
PUD
PUD: PULL-UP DISABLE