Datasheet

140
ATmega323(L)
1457E–11/01
Figure 70. Port B Schematic Diagram (Pin PB3)
Figure 71. Port B Schematic Diagram (Pin PB4)
PB3
DDB3
PORTB3
COMP. MATCH 0
COM00
COM01
WP:
WD:
RL:
RP:
RD:
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
FOC0
PWM0
PUD: PULL-UP DISABLE
PUD
AIN1
TO COMPARATOR
PWRDN
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PB4
SPI SS
MSTR
SPE
WP:
WD:
RL:
RP:
RD:
MSTR:
SPE:
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI MASTER ENABLE
SPI ENABLE
DDB4
PORTB4
RL
RP
PUD
PUD: PULL-UP DISABLE