Datasheet

139
ATmega323(L)
1457E–11/01
Figure 68. Port B Schematic Diagram (Pin PB1)
Figure 69. Port B Schematic Diagram (Pin PB2)
PUD
PUD: PULL-UP DISABLE
PB1
PORTB1
DDB1
TIMER1 CLOCK
SOURCE MUX
CS12 CS11 CS10
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PB2
R
R
WP:
WD:
RL:
RP:
RD:
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
DDB2
PORTB2
RL
RP
DQ
C
R
ISC2
'1'
INT2
SW CLEAR
HW CLEAR
PUD
PUD: PULL-UP DISABLE
AIN0
TO COMPARATOR
INT2 ENABLE
PWRDN