Datasheet

138
ATmega323(L)
1457E–11/01
OC0, Output compare match output: The PB3 pin can serve as an external output for
the Timer/Counter0 compare match. The PB3 pin has to be configured as an output
(DDB3 set (one)) to serve this function. See “8-bit Timers/Counters T/C0 and T/C2” on
page 44 for further details, and how to enable the output. The OC0 pin is also the output
pin for the PWM mode timer function.
• AIN0/INT2 - Port B, Bit 2
AIN0, Analog Comparator Positive Input. When configured as an input (DDB2 is cleared
(zero)) and with the internal MOS pull up resistor switched off (PB2 is cleared (zero)),
this pin also serves as the positive input of the On-chip analog comparator. During
power-down mode, the schmitt trigger of the digital input is disconnected if INT2 is not
enabled. This allows analog signals which are close to V
CC
/2 to be present during
power-down without causing excessive power consumption.
INT2, External Interrupt source 2: The PB2 pin can serve as an external interrupt source
to the MCU. See “MCU Control and Status Register – MCUCSR” on page 30 for further
details.
• T1 - Port B, Bit 1
T1, Timer/Counter1 counter source. See the timer description for further details.
• T0/XCK - Port B, Bit 0
T0, Timer/Counter0 counter source. See the timer description for further details.
XCK, USART external clock. See the USART description for further details.
Port B Schematics Note that all port pins are synchronized. The synchronization latches are not shown in
the figures.
Figure 67. Port B Schematic Diagram (Pin PB0)
PUD
PUD: PULL-UP DISABLE
UMSEL
XCK OUTPUT
XCK INPUT
PB0
CS02 CS01 CS00
TIMER0 CLOCK
SOURCE MUX
PORTB0
DDB0
1
0