Datasheet

137
ATmega323(L)
1457E–11/01
Port B pins are tri-stated when a reset condition becomes active, even if the clock is not
running.
Note: n: 7,6…0, pin number.
Alternate Functions of Port B The alternate pin configuration is as follows:
• SCK - Port B, Bit 7
SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is
enabled as a slave, this pin is configured as an input regardless of the setting of DDB7.
When the SPI is enabled as a master, the data direction of this pin is controlled by
DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB7 bit. See the description of the SPI port for further details.
• MISO - Port B, Bit 6
MISO: Master data input, slave data output pin for SPI channel. When the SPI is
enabled as a master, this pin is configured as an input regardless of the setting of
DDB6. When the SPI is enabled as a slave, the data direction of this pin is controlled by
DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB6 bit. See the description of the SPI port for further details.
• MOSI - Port B, Bit 5
MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is
enabled as a slave, this pin is configured as an input regardless of the setting of DDB5.
When the SPI is enabled as a master, the data direction of this pin is controlled by
DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB5 bit. See the description of the SPI port for further details.
• SS
- Port B, Bit 4
SS
: Slave port select input. When the SPI is enabled as a slave, this pin is configured as
an input regardless of the setting of DDB4. As a slave, the SPI is activated when this pin
is driven low. When the SPI is enabled as a master, the data direction of this pin is con-
trolled by DDB4. When the pin is forced to be an input, the pull-up can still be controlled
by the PORTB4 bit. See the description of the SPI port for further details.
• AIN1/OC0 - Port B, Bit 3
AIN1, Analog Comparator Negative Input. When configured as an input (DDB3 is
cleared (zero)) and with the internal MOS pull up resistor switched off (PB3 is cleared
(zero)), this pin also serves as the negative input of the On-chip analog comparator.
During power-down mode, the schmitt trigger of the digital input is disconnected. This
allows analog signals which are close to V
CC
/2 to be present during power-down without
causing excessive power consumption.
Table 50. DDBn Effects on Port B Pins
DDBn PORTBn
PUD
(in SFIOR) I/O Pull-up Comment
0 0 X Input No Tri-state (Hi-Z)
0 1 0 Input Yes
PBn will Source Current if Ext. Pulled
Low.
0 1 1 Input No Tri-state (Hi-Z)
1 0 X Output No Push-Pull Zero Output
1 1 X Output No Push-Pull One Output