Datasheet

135
ATmega323(L)
1457E–11/01
PUD bit has to be set. The Port A pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Note: n: 7,6…0, pin number.
Port A Schematics Note that all port pins are synchronized. The synchronization latches are not shown in
the figure.
Figure 66. Port A Schematic Diagrams (Pins PA0 - PA7)
Port B Port B is an 8-bit bi-directional I/O port with optional internal pull-ups.
Three I/O memory address locations are allocated for Port B, one each for the Data
Register – PORTB, $18($38), Data Direction Register – DDRB, $17($37) and the Port B
Input Pins
– PINB, $16($36). The Port B Input Pins address is read only, while the Data
Register and the Data Direction Register are read/write.
All port pins have individually selectable pull-up resistors. The Port B output buffers can
sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7 are used as
Table 48. DDAn Effects on Port A Pins
DDAn PORTAn
PUD
(in SFIOR) I/O Pull Up Comment
0 0 X Input No Tri-state (Hi-Z)
0 1 0 Input Yes
PAn will source current if ext. pulled
low.
0 1 1 Input No Tri-state (Hi-Z)
1 0 X Output No Push-pull Zero Output
1 1 X Output No Push-pull One Output
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PDn
ADCn
TO ADC MUX
WP:
WD:
RL:
RP:
RD:
n:
WRITE PORTA
WRITE DDRA
READ PORTA LATCH
READ PORTA PIN
READ DDRA
0-7
DDAn
PORTAn
RL
RP
PWRDN
PUD
PUD: PULL-UP DISABLE