Datasheet

131
ATmega323(L)
1457E–11/01
The ADC Data Register –
ADCL and ADCH
ADLAR = 0:
ADLAR = 1:
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Conse-
quently, if the result is left adjusted and no more than 8 bit precision is required, it is
sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX affects the way the result is read from the registers. If ADLAR
is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted.
• ADC9..0: ADC Conversion Result
These bits represent the result from the conversion. $000 represents analog ground,
and $3FF represents the selected reference voltage minus one LSB.
Scanning Multiple
Channels
Since change of analog channel always is delayed until a conversion is finished, the
Free Running Mode can be used to scan multiple channels without interrupting the con-
verter. Typically, the ADC Conversion Complete interrupt will be used to perform the
channel shift. However, the user should take the following fact into consideration:
The interrupt triggers once the result is ready to be read. In Free Running Mode, the
next conversion will start immediately when the interrupt triggers. If ADMUX is changed
after the interrupt triggers, the next conversion has already started, and the old setting is
used.
10132
11064
1 1 1 128
Table 47. ADC Prescaler Selections (Continued)
ADPS2 ADPS1 ADPS0 Division Factor
Bit 151413121110 9 8
$05 ($25)
SIGN-----ADC9 ADC8 ADCH
$04 ($24) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
76543210
Read/WriteRRRRRRRR
RRRRRRRR
Initial Value00000000
00000000
Bit 151413121110 9 8
$05 ($25)
ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
$04 ($24) ADC1 ADC0 ------ADCL
76543210
Read/WriteRRRRRRRR
RRRRRRRR
Initial Value00000000
00000000