Datasheet

128
ATmega323(L)
1457E–11/01
Figure 64. ADC Timing Diagram, Free Run Conversion
ADC Noise Canceler
Function
The ADC features a noise canceler that enables conversion during ADC Noise Reduc-
tion mode (see “Sleep Modes” on page 38) to reduce noise induced from the CPU core
and other I/O peripherals. If other I/O peripherals must be active during conversion, this
mode works equivalently for Idle mode. To make use of this feature, the following proce-
dure should be used:
1. Make sure that the ADC is enabled and is not busy converting. Single Conver-
sion Mode must be selected and the ADC conversion complete interrupt must be
enabled.
ADEN = 1
ADSC = 0
ADFR = 0
ADIE = 1
2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conver-
sion once the CPU has been halted.
3. If no other interrupts occur before the ADC conversion completes, the ADC inter-
rupt will wake up the CPU and execute the ADC Conversion Complete interrupt
routine.
The ADC Multiplexer Selection
Register – ADMUX
Table 44. ADC Conversion Time
Condition
Sample & Hold (Cycles from
Start of Conversion)
Conversion
Time (Cycles)
Conversion
Time (µs)
Extended Conversion 13.5 25 125 - 500
Normal Conversions 1.5 13 65 - 260
11 12 13
Sign and MSB of result
LSB of result
ADC clock
ADSC
ADIF
ADCH
ADCL
Cycle number
12
One Conversion Next Conversion
34
Conversion
complete
Sample & hold
MUX and REFS
update
Bit 76543210
$07 ($27)
REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADMUX
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000