Datasheet

122
ATmega323(L)
1457E–11/01
• Bit 4 - ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE
bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, ACI is cleared by
writing a logic one to the flag.
• Bit 3 - ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the ana-
log comparator interrupt is activated. When cleared (zero), the interrupt is disabled.
• Bit 2 - ACIC: Analog Comparator Input Capture Enable
When set (one), this bit enables the Input Capture function in Timer/Counter1 to be trig-
gered by the analog comparator. The comparator output is in this case directly
connected to the Input Capture front-end logic, making the comparator utilize the noise
canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When
cleared (zero), no connection between the analog comparator and the Input Capture
function is given. To make the comparator trigger the Timer/Counter1 Input Capture
interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one).
• Bits 1,0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator inter-
rupt. The different settings are shown in Table 42.
When changing the ACIS1/ACIS0 bits, The Analog Comparator Interrupt must be dis-
abled by clearing its Interrupt Enable bit in the ACSR register. Otherwise an interrupt
can occur when the bits are changed.
Table 42. ACIS1/ACIS0 Settings
ACIS1 ACIS0 Interrupt Mode
0 0 Comparator Interrupt on Output Toggle
01Reserved
1 0 Comparator Interrupt on Falling Output Edge
1 1 Comparator Interrupt on Rising Output Edge