Datasheet

11
ATmega323(L)
1457E–11/01
The General-purpose
Register File
Figure 7 shows the structure of the 32 general-purpose working registers in the CPU.
Figure 7. AVR CPU General-purpose Working Registers
Most register operating instructions in the instruction set have direct access to all regis-
ters, and most of them are single cycle instructions.
As shown in Figure 7, each register is also assigned a data memory address, mapping
them directly into the first 32 locations of the user Data Space. Although not being phys-
ically implemented as SRAM locations, this memory organization provides great
flexibility in access of the registers, as the X, Y, and Z registers can be set to index any
register in the file.
The X-register, Y-register, and
Z-register
The registers R26..R31 have some added functions to their general-purpose usage.
These registers are address pointers for indirect addressing of the Data Space. The
three indirect address registers X, Y, and Z are defined as:
Figure 8. The X, Y, and Z Registers
In the different addressing modes these address registers have functions as fixed dis-
placement, automatic increment and decrement (see the descriptions for the different
instructions).
7 0 Addr.
R0 $00
R1 $01
R2 $02
…
R13 $0D
General R14 $0E
Purpose R15 $0F
Working R16 $10
Registers R17 $11
…
R26 $1A X-register low byte
R27 $1B X-register high byte
R28 $1C Y-register low byte
R29 $1D Y-register high byte
R30 $1E Z-register low byte
R31 $1F Z-register high byte
15 XH XL 0
X - register 70
0 7 0
R27 ($1B) R26 ($1A)
15 YH YL 0
Y - register 70
0 7 0
R29 ($1D) R28 ($1C)
15 ZH ZL 0
Z - register 70
0 7 0
R31 ($1F) R30 ($1E)