Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • – 130 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General-purpose Working Registers – Fully Static Operation – Up to 8 MIPS Throughput at 8 MHz – On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories – 32K Bytes of In-System Self-programmable Flash Endurance: 1,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming
Pin Configurations PDIP (XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP) PD6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF AGND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 (TDI) PC4 (TDO) PC3 (TMS) PC2 (TCK) PC1 (SDA) PC0
ATmega323(L) Overview The ATmega323 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega323 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 1. Block Diagram PA0 - PA7 PC0 - PC7 PORTA DRIVERS PORTC DRIVERS VCC GND DATA DIR. REG. PORTA DATA REGISTER PORTA DATA REGISTER PORTC DATA DIR. REG.
The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega323(L) pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega323 as listed on page 135. Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers can sink 20 mA.
Clock Options The device has the following clock source options, selectable by Flash fuse bits as shown: Table 1. Device Clocking Options Select Device Clocking Option CKSEL3..0 External Crystal/Ceramic Resonator 1111 - 1010 External Low-frequency Crystal 1001 - 1000 External RC Oscillator 0111 - 0101 Internal RC Oscillator 0100 - 0010 External Clock 0001 - 0000 Note: “1” means unprogrammed, “0” means programmed.
ATmega323(L) External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 3. Figure 3. External Clock Drive Configuration External RC Oscillator For timing insensitive applications, the external RC configuration shown in Figure 4 can be used. For details on how to choose R and C, see Table 73 on page 209. Figure 4.
Architectural Overview The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file – in one clock cycle.
ATmega323(L) Figure 5.
The 2K bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance with their interrupt vector position.
ATmega323(L) The General-purpose Register File Figure 7 shows the structure of the 32 general-purpose working registers in the CPU. Figure 7. AVR CPU General-purpose Working Registers 7 0 Addr.
The ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. ATmega323 also provides a powerful multiplier supporting both signed/unsigned multiplication and fractional format.
ATmega323(L) Figure 9. SRAM Organization Register File Data Address Space R0 R1 R2 ... $0000 $0001 $0002 ... R29 R30 R31 I/O Registers $00 $01 $02 ... $001D $001E $001F $3D $3E $3F $005D $005E $005F Internal SRAM $0060 $0061 ... $0020 $0021 $0022 ... $085E $085F The Program and Data Addressing Modes The ATmega323 AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to the program memory (Flash) and data memory (SRAM, Register File, and I/O Memory).
Register Direct, Two Registers Rd and Rr Figure 11. Direct Register Addressing, Two Registers Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). I/O Direct Figure 12. I/O Direct Addressing Operand address is contained in 6-bits of the instruction word. n is the destination or source register address. Data Direct Figure 13.
ATmega323(L) Data Indirect with Displacement Figure 14. Data Indirect with Displacement Data Space $0000 15 0 Y OR Z - REGISTER 15 10 OP 6 5 n 0 a $085F Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instruction word. Data Indirect Figure 15. Data Indirect Addressing Data Space $0000 15 0 X, Y OR Z - REGISTER $085F Operand address is the contents of the X, Y-, or the Z-register. Data Indirect with Pre-decrement Figure 16.
Data Indirect with Post-increment Figure 17. Data Indirect Addressing With Post-increment Data Space $0000 15 0 X, Y OR Z - REGISTER 1 $085F The X-, Y-, or the Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or the Z-register prior to incrementing. Constant Addressing Using Figure 18. Code Memory Constant Addressing the LPM and SPM Instructions $3FFF Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 16K).
ATmega323(L) Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register). Relative Program Addressing, RJMP and RCALL Figure 20. Relative Program Memory Addressing 1 $3FFF Program execution continues at address PC + k + 1. The relative address k is from – 2048 to 2047. The EEPROM Data Memory The ATmega323 contains 1K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written.
Figure 22 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 22. Single Cycle ALU Operation T1 T2 T3 T4 System Clock Ø Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back The internal data SRAM access is performed in two System Clock cycles as described in Figure 23. Figure 23.
ATmega323(L) Table 2.
Table 2.
ATmega323(L) flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. The I/O and peripherals control registers are explained in the following sections.
The Stack Pointer – SP The ATmega323 Stack Pointer is implemented as two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the ATmega323 data memory has $860 locations, 12 bits are used.
ATmega323(L) Table 3. Reset and Interrupt Vectors (Continued) Vector No.
$01a jmp USART_RXC $01c jmp USART_UDRE ; UDR Empty Handler ; USART RX Complete Handler $01e jmp USART_TXC ; USART TX Complete Handler $020 jmp ADC ; ADC Conversion Complete Interrupt Handler $022 jmp EE_RDY ; EEPROM Ready Handler $024 jmp ANA_COMP ; Analog Comparator Handler $026 jmp TWSI ; 2-wire Serial Interface Interrupt Handler ; $028 MAIN: ldi $029 out SPH,r16 $02a ldi r16,low(RAMEND) $02b out SPL,r16 $02c ... ...
ATmega323(L) When the BOOTRST fuse is programmed, the boot section size set to 4K bytes and the IVSEL bit in the GICR register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses are: Address Labels Code $000 MAIN: Comments ldi r16,high(RAMEND); Main program start $001 out SPH,r16 $002 ldi r16,low(RAMEND) $003 out SPL,r16 $004 ; Set stack pointer to top of RAM xxx ; Reset Sources .
Figure 24. Reset Logic DATA BUS PORF BORF EXTRF WDRF JTRF MCU Control and Status Register (MCUCSR) Brown-Out Reset Circuit BODEN BODLEVEL 100-500kΩ SPIKE FILTER JTAG Reset Register Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] Table 5. Reset Characteristics(1) Symbol VPOT Min Typ Max Units Power-on Reset Threshold Voltage (rising) 1.0 1.4 1.8 V Power-on Reset Threshold Voltage (falling)(2) 0.4 0.6 0.8 V - - 0.85 VCC V (BODLEVEL = 1) 2.4 2.7 3.2 (BODLEVEL = 0) 3.
ATmega323(L) Table 6. Reset Delay Selections(1) CKSEL(2) 0000 0001 0010 Start-up Time, VCC = 2.7V, BODLEVEL Unprogrammed Start-up Time, VCC = 4.0V, BODLEVEL Programmed 4.2 ms + 6 CK 5.8 ms + 6 CK Ext. Clock, Fast Rising Power 30 µs + 6 CK(4) 10 µs + 6 CK(5) Ext. Clock, BOD Enabled 67 ms + 6 CK 92 ms + 6 CK Int. RC Oscillator, Slowly Rising Power 4.2 ms + 6 CK 5.8 ms + 6 CK Int. RC Oscillator, Fast Rising Power 30 µs + 6 CK(4) 10 µs + 6 CK(5) Int.
Table 6 shows the start-up times from reset. When the CPU wakes up from power-down or power-save, only the clock counting part of the start-up time is used. The Watchdog oscillator is used for timing the real-time part of the start-up time. The number WDT oscillator cycles used for each time-out is shown in Table 7. The frequency of the Watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section.
ATmega323(L) Figure 26. MCU Start-up, RESET Extended Externally VCC RESET VPOT VRST TIME-OUT tTOUT INTERNAL RESET External Reset An external reset is generated by a low level on the RESET pin. Reset pulses longer than 500 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST on its positive edge, the delay timer starts the MCU after the Time-out period tTOUT has expired.
Figure 28. Brown-out Reset During Operation VCC VBOT+ VBOT- RESET tTOUT TIME-OUT INTERNAL RESET The hysteresis on VBOT: VBOT+ = VBOT + 25 mV, VBOT- = VBOT - 25 mV Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 63 for details on operation of the Watchdog Timer. Figure 29.
ATmega323(L) (zero), a falling edge on INT2 activates the interrupt. If ISC2 is set (one) a rising edge on INT2 activates the interrupt. Edges on INT2 are registered asynchronously. Pulses on INT2 wider than 50 ns will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. When changing the ISC2 bit, an interrupt can occur. Therefore, it is recommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR register. Then, the ISC2 bit can be changed.
power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering power-down mode. Interrupt Handling The ATmega323 has two 8-bit Interrupt Mask control registers: GICR – General Interrupt Control register and TIMSK – Timer/Counter Interrupt Mask register. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
ATmega323(L) corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector. See also “External Interrupts” on page 36. • Bit 6 - INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated.
The General Interrupt Flag Register – GIFR Bit 7 6 5 4 3 2 1 $3A ($5A) INTF1 INTF0 INTF2 - - - - 0 - Read/Write R/W R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 GIFR • Bit 7 - INTF1: External Interrupt Flag1 When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GICR are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when the interrupt routine is executed.
ATmega323(L) • Bit 4 - OCIE1A: Timer/Counter1 Output CompareA Match Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 5 - ICF1: Input Capture Flag 1 The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register – ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and the ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.
ATmega323(L) is enabled and is configured as level triggered (only INT0/INT1), the interrupt will trigger as long as the pin is held low. MCU Control Register – MCUCR The MCU Control Register contains control bits for general MCU functions.
• Bit 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 10. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt.
ATmega323(L) In future devices this is subject to change. It is recommended for future code compatibility to disable Timer/Counter2 interrupts during ADC Noise Reduction mode if the Timer/Counter2 is clocked synchronously. Power-down Mode When the SM2..0 bits are 010, the SLEEP instruction makes the MCU enter Powerdown mode. In this mode, the external oscillator is stopped, while the external interrupts, the 2-wire Serial Interface address watch, and the Watchdog continue operating (if enabled).
Calibrated Internal RC Oscillator Oscillator Calibration Register – OSCCAL The calibrated internal oscillator provides a fixed 1.0 MHz (nominal) clock at 5V and 25°C. This clock may be used as the system clock. See the section “Clock Options” on page 6 for information on how to select this clock as the system clock. This oscillator can be calibrated by writing the calibration byte to the OSCCAL register.
ATmega323(L) • Bit 1 - PSR2: Prescaler Reset Timer/Counter2 When this bit is set (one) the Timer/Counter2 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset.
Timer/Counters The ATmega323 provides three general-purpose Timer/Counters – two 8-bit T/Cs and one 16-bit T/C. Timer/Counter2 can optionally be asynchronously clocked from an external oscillator. This oscillator is optimized for use with a 32.768 kHz watch crystal, enabling use of Timer/Counter2 as a Real Time Counter (RTC). Timer/Counters 0 and 1 have individual prescaling selection from the same 10-bit prescaler. Timer/Counter2 has its own prescaler.
ATmega323(L) Figure 31. Prescaler for Timer/Counter2 PSR2 PCK2/1024 PCK2/256 PCK2/128 AS2 PCK2/64 10-BIT T/C PRESCALER Clear PCK2/32 XTAL1 PCK2 PCK2/8 CK 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE TCK2 The clock source for Timer/Counter2 is named PCK2. PCK2 is by default connected to the main system clock CK. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the PC6(TOSC1) pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC).
8-bit Timers/Counters T/C0 and T/C2 Figure 32 shows the block diagram for Timer/Counter0. Figure 33 shows the block diagram for Timer/Counter2. Figure 32. Timer/Counter0 Block Diagram 7 0 TIMER/COUNTER0 (TCNT0) 7 PSR2 PSR10 SPECIAL FUNCTIONS IO REGISTER (SFIOR) CS00 CS01 CS02 CTC0 COM00 COM01 FOC0 PWM0 T/C0 CONTROL REGISTER (TCCR0) TOV0 TOV1 OCF0 OCF1B ICF1 OCF1A TOV2 TIMER INT. FLAG REGISTER (TIFR) OCF2 TIMER INT.
ATmega323(L) Figure 33. Timer/Counter2 Block Diagram T/C2 OVER- T/C2 COMPARE FLOW IRQ MATCH IRQ 8-BIT DATA BUS 7 0 TIMER/COUNTER2 (TCNT2) PSR2 CS20 CS21 CS22 CTC2 COM20 COM21 FOC2 PWM2 PSR10 SPECIAL FUNCTIONS IO REGISTER (SFIOR) T/C2 CONTROL REGISTER (TCCR2) T/C CLEAR T/C CLK SOURCE UP/DOWN 7 TOV0 TOV1 OCF0 OCF1B OCF1A ICF1 TOV2 TIMER INT. FLAG REGISTER (TIFR) OCF2 TIMER INT.
Timer/Counter0 and 2 can also be used as 8-bit Pulse Width Modulators. In this mode, the Timer/Counter and the output compare register serve as a glitch-free, stand-alone PWM with centered pulses. Refer to page 48 for a detailed description on this function.
ATmega323(L) • Bit 3 - CTC0/CTC2: Clear Timer/Counter on Compare Match When the CTC0 or CTC2 control bit is set (one), Timer/Counter0 or Timer/Counter2 is reset to $00 in the CPU clock cycle following a compare match. If the control bit is cleared, the Timer/Counter continues counting and is unaffected by a compare match. When a prescaling of 1 is used, and the compare register is set to C, the timer will count as follows if CTC0/CTC2 is set: ... | C-1 | C | 0 | 1 | ...
PB0(T0) will clock the counter even if the pin is configured as an output. This feature can give the user SW control of the counting.
ATmega323(L) PWM Modes (Up/Down and Overflow) The two different PWM modes are selected by the CTC0 or CTC2 bit in the Timer/Counter Control Registers -TCCR0 or TCCR2 respectively. If CTC0/CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero before the cycle is repeated.
Figure 34. Effects of Unsynchronized OCR Latching in Up/Down Mode Compare Value changes Counter Value Compare Value PWM Output OCn Synchronized OCn Latch Compare Value changes Counter Value Compare Value PWM Output OCn Unsynchronized OCn Latch Glitch Figure 35.
ATmega323(L) Table 16. PWM Outputs OCRn = $00 or $FF COMn1 COMn0 OCRn Output PWMn 1 0 $00 L 1 0 $FF H 1 1 $00 H 1 1 $FF L Note: n = 0 or 2 In overflow PWM mode, the table above is only valid for OCRn = $FF. In up/down PWM mode, the Timer Overflow Flag, TOV0 or TOV2, is set when the counter advances from $00. In overflow PWM mode, the Timer Overflow Flag is set as in normal Timer/Counter mode. Timer Overflow Interrupt0 and 2 operate exactly as in normal Timer/Counter mode, i.e.
• If a write is performed to any of the three Timer/Counter2 registers while its update busy flag is set (one), the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is read.
ATmega323(L) power-up reset or wake-up from Power-down or Standby mode, the user should be aware of the fact that this oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after powerup or wake-up from Power-down or Standby mode.
Register B – TCCR1B” on page 56. The different status flags (overflow, compare match, and capture event) are found in the Timer/Counter Interrupt Flag Register – TIFR. Control signals are found in the Timer/Counter1 Control Registers – TCCR1A and TCCR1B. The interrupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register – TIMSK. When Timer/Counter1 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU.
ATmega323(L) Timer/Counter1 Control Register A – TCCR1A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B PWM11 PWM10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 $2F ($4F) TCCR1A • Bits 7,6 - COM1A1, COM1A0: Compare Output Mode1A, bits 1 and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A – Output CompareA.
bit will always be read as zero. The setting of the FOC1B bit has no effect in PWM mode. • Bits 1..0 - PWM11, PWM10: Pulse Width Modulator Select Bits These bits select PWM operation of Timer/Counter1 as specified in Table 11. This mode is described on page 59. Table 18.
ATmega323(L) • Bits 2..0 - CS12, CS11, CS10: Clock Select1, Bit 2,1, and 0 The Clock Select1 bits 2, 1, and 0 define the prescaling source of Timer/Counter1. Table 19. Clock 1 Prescale Select CS12 CS11 CS10 Description 0 0 0 Stop, the Timer/Counter1 is Stopped. 0 0 1 CK 0 1 0 CK/8 0 1 1 CK/64 1 0 0 CK/256 1 0 1 CK/1024 1 1 0 External Pin T1, Falling Edge 1 1 1 External Pin T1, Rising Edge The Stop condition provides a Timer Enable/Disable function.
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value.
ATmega323(L) Timer/Counter1 Input Capture Register – ICR1H and ICR1L Bit 15 $27 ($47) 14 13 12 11 10 9 ICR1H LSB $26 ($46) 7 Read/Write 8 MSB 6 5 4 3 2 1 R R R R R R R R R R R R R R R R Initial Value ICR1L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The input capture register is a 16-bit read-only register.
As shown in Table 20, the PWM operates at either 8, 9, or 10 bits resolution. Note the unused bits in OCR1A, OCR1B, and TCNT1 will automatically be written to zero by hardware. I.e. bit 9 to 15 will be set to zero in OCR1A, OCR1B, and TCNT1 if the 9-bit PWM resolution is selected. This makes it possible for the user to perform read-modifywrite operations in any of the three resolution modes and the unused bits will be treated as don’t care. Table 21.
ATmega323(L) Figure 38. Effects of Unsynchronized OCR1 Latching. PWM Output OC1x Synchronized OC1x Latch PWM Output OC1x Unsynchronized OC1x Latch Note: x = A or B Figure 39. Effects of Unsynchronized OCR1 Latching in Overflow Mode PWM Output OC1x Synchronized OC1x Latch PWM Output OC1x Unsynchronized OC1x Latch Note: X = A or B During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location.
Table 23. PWM Outputs OCR1X = $0000 or TOP COM1X1 COM1X0 OCR1X Output OC1X 1 0 $0000 L 1 0 TOP H 1 1 $0000 H 1 1 TOP L In overflow PWM mode, the table above is only valid for OCR1X = TOP. In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter advances from $0000. In overflow PWM mode, the Timer Overflow flag is set as in normal Timer/Counter mode. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode, i.e.
ATmega323(L) Watchdog Timer The Watchdog Timer is clocked from a separate On-chip oscillator which runs at 1 Mhz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 24 on page 64. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period.
1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the Watchdog. • Bits 2..0 - WDP2, WDP1, WDP0: Watch Dog Timer Prescaler 2, 1, and 0 The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.
ATmega323(L) EEPROM Read/Write Access The EEPROM access registers are accessible in the I/O space. The write access time is in the range of 1.9 - 3.8 ms, depending on the frequency of the calibrated RC oscillator. See Table 25 for details. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some precautions must be taken.
The EEPROM Control Register – EECR Bit 7 6 5 4 3 2 1 0 $1C ($3C) - - - - EERIE EEMWE EEWE EERE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 X 0 EECR • Bits 7..4 - Res: Reserved Bits These bits are reserved bits in the ATmega323 and will always read as zero. • Bit 3 - EERIE: EEPROM Ready Interrupt Enable When the I bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled.
ATmega323(L) The calibrated oscillator is used to time the EEPROM accesses. Table 25 lists the typical programming time for EEPROM access from the CPU. Table 25. EEPROM Programming Time. Symbol EEPROM write (from CPU) Preventing EEPROM Corruption Number of Calibrated RC Oscillator Cycles Min Programming Time Max Programming Time 2048 1.9 ms 3.8 ms During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly.
Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega323 and peripheral devices or between several AVR devices.
ATmega323(L) Figure 42. SPI Master-slave Interconnection MSB MASTER LSB MISO MISO 8 BIT SHIFT REGISTER SPI CLOCK GENERATOR MSB MASTER LSB 8 BIT SHIFT REGISTER MOSI MOSI SCK SCK SS VCC SS The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed.
once the SS pin is driven high. If the SS pin is driven high during a transmission, the SPI will stop sending and receiving immediately and both data received and data sent must be considered as lost. Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 43 and Figure 44. Figure 43.
ATmega323(L) • Bit 4 - MSTR: Master/Slave Select This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to reenable SPI master mode. • Bit 3 - CPOL: Clock Polarity When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle.
• Bit 0 - SPI2X: Double SPI Speed Bit When this bit is set (one) the SPI speed (SCK Frequency) will be doubled when the SPI is in master mode (see Table 27). This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fck/4 or lower. The SPI interface on the ATmega323 is also used for program memory and EEPROM downloading or uploading. See page 191 for serial programming and verification.
ATmega323(L) USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device.
XCK (transfer clock) pin is only used by synchronous transfer mode. The transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame formats. The write buffer allows a continuous transfer of data without any delay between frames. The receiver is the most complex part of the USART module due to its clock and data recovery units. The recovery units are used for asynchronous data reception.
ATmega323(L) Clock Generation The clock generation logic generates the base clock for the transmitter and receiver. The USART supports four modes of clock operation: normal asynchronous, double speed asynchronous, master synchronous and slave synchronous mode. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation. Double speed (asynchronous mode only) is controlled by the U2X found in the UCSRA register.
Table 29 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRR value for each mode of operation using an internally generated clock source. Table 29.
ATmega323(L) Figure 47. Synchronous Mode XCK Timing UCPOL = 0 XCK RxD / TxD Sample UCPOL = 1 XCK RxD / TxD Sample The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As Figure 47 shows, when UCPOL is zero the data will be changed at falling XCK edge and sampled at rising XCK edge. If UCPOL is set, the data will be changed at rising XCK edge and sampled at falling XCK edge.
changing the setting of any of these bits will corrupt all ongoing communication for both the receiver and transmitter. The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame. The USART Parity Mode (UPM1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the USART Stop Bit Select (USBS) bit. The receiver ignores the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the first stop bit is zero.
ATmega323(L) Assembly Code Example(1) USART_Init: ; Set baud rate out UBRRH, r17 out UBRRL, r16 ; Enable receiver and transmitter ldi r16, (1<>8); UBRRL = (unsigned char)baud; /* Enable receiver and transmitter */ UCSRB = (1<
The following code examples show a simple USART transmit function based on polling of the Data Register Empty (UDRE) flag. When using frames with less than eight bit, the most significant bits written to the UDR are ignored. The USART has to be initialized before the function can be used. For the assembly code, the data to be sent is assumed to be stored in Register R16.
ATmega323(L) Sending Frames with 9 Data Bit If 9 bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character written to UDR. The following code examples show a transmit function that handles 9 bit characters. For the assembly code, the data to be sent is assumed to be stored in Registers R17:R16.
The Transmit Complete (TXC) flag bit is set one when the entire frame in the transmit shift register has been shifted out and there are no new data currently present in the transmit buffer. The TXC flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location.
ATmega323(L) Data Reception – The USART Receiver The USART receiver is enabled by setting the Receive Enable (RXEN) bit in the UCSRB register. When the receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCK pin will be used as transfer clock.
Receiving Frames with 9 Data Bits If 9 bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and PE status flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR and PE bits, which all are stored in the FIFO, will change.
ATmega323(L) The receive function example reads all the I/O registers into the register file before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. Receive Compete Flag and Interrupt The USART receiver has one flag that indicates the receiver state. The Receive Complete (RXC) flag indicates if there are unread data present in the receive buffer.
The PE bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. Disabling the Receiver In contrast to the transmitter, disabling the of the receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e.
ATmega323(L) Figure 49. Start Bit Sampling RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure.
Figure 51. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2X = 1) 1 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the frame error (FE) flag will be set. A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting.
ATmega323(L) Table 30 and Table 31 list the maximum receiver baud rate error that can be tolerated. Note that normal speed mode has higher toleration of baud rate variations. Table 30. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) D# (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.
If the receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indicates if the frame contain data or address information. If the receiver is set up for frames with 9 data bits, then the 9th bit (RXB8) is used for identifying address and data frames. When the frame type bit (the first stop or the 9th bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame.
ATmega323(L) Accessing UBRRH/UCSRC Registers The UBRRH register shares the same I/O location as the UCSRC register. Therefore some special consideration must be taken when accessing this I/O location. Write Access When doing a write access of this I/O location, the high bit of the value written, the USART Register Select (URSEL) bit, controls which one of the two registers that will be written. If URSEL is zero during a write operation, the UBRRH value will be updated.
Read Access Doing a read access to the UBRRH or the UCSRC register is a more complex operation. However, in most applications, it is rarely necessary to read any of these registers. The read access is controlled by a timed sequence. Reading the I/O location once returns the UBRRH register contents. If the register location was read in previous system clock cycle, reading the register in the current clock cycle will return the UCSRC contents.
ATmega323(L) USART Register Description USART I/O Data Register – UDR Bit 7 6 5 4 3 2 1 0 $0C ($2C) Read RXB[7:0] UDR (Read) $0C ($2C) Write TXB[7:0] UDR (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer register and USART Receive Data Buffer registers share the same I/O address referred to as USART Data Register or UDR.
• Bit 4 - FE: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e. when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRA. • Bit 3 - DOR: Data OverRun This bit is set if a data overrun condition is detected.
ATmega323(L) • Bit 3 - TXEN: Transmitter Enable Setting this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (setting the TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled the transmitter will no longer override the TxD port.
Table 33. Parity Mode UPM1 UPM0 Parity Mode 0 0 Disabled 0 1 (Reserved) 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity • Bit 3 - USBS: Stop Bit Select This bit selects number of stop bits to be inserted by the transmitter. The receiver ignores this setting. Table 34.
ATmega323(L) USART Baud Rate Registers – UBRRL and UBRRHs Bit $20 ($40) 15 14 13 12 URSEL - - - 7 Initial Value 10 9 8 UBRR[11:8] UBRRH UBRR[7:0] $09 ($29) Read/Write 11 6 5 4 3 UBRRL 2 1 0 R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The UBRRH register shares the same I/O location as the UCSRC register.
Table 36. Examples of UBRR Settings for Commonly Used Oscillator Frequencies – UBRR = 0, Error = 0.0% fosc = 1.0000 MHz fosc = 1.8432 MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 14.4K 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 19.2K 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 28.8K 1 8.5% 3 8.5% 3 0.0% 7 0.0% 38.4K 1 -18.6% 2 8.5% 2 0.
ATmega323(L) Table 36. Examples of UBRR Settings for Commonly Used Oscillator Frequencies – UBRR = 0, Error = 0.0% (Continued) fosc = 4.0000 MHz fosc = 7.3728 MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error 2400 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4K 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2K 12 0.2% 25 0.2% 23 0.0% 47 0.0% 28.8K 8 -3.5% 16 2.1% 15 0.
2-wire Serial Interface (Byte Oriented) The 2-wire Serial Interface supports bi-directional serial communication. It is designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs connected to them. Various communication configurations can be designed using this bus. Figure 52 shows a typical 2-wire Serial Bus configuration.
ATmega323(L) Figure 54.
• Bits 7..0 - 2-wire Serial Interface Bit Rate Register TWBR selects the division factor for the bit rate generator.
ATmega323(L) 2-wire Serial Interface waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master status. • Bit 4 - TWSTO: 2-wire Serial Bus STOP Condition Flag TWSTO is a stop condition flag. In Master mode setting the TWSTO bit in the control register will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically.
The 2-wire Serial Interface Data Register – TWDR Bit 7 6 5 4 3 2 1 0 TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 $03 ($23) TWDR • Bits 7..0 - TWD: 2-wire Serial Interface Data Register These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the 2-wire Serial Bus. In transmit mode, TWDR contains the next byte to be transmitted.
ATmega323(L) W: Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P: STOP condition SLA: Slave Address In Figure 55 to Figure 58, circles are used to indicate that the 2-wire Serial Interface interrupt flag is set. The numbers in the circles show the status code held in TWSR. At these points, actions must be taken by the application to continue or complete the 2-wire Serial Bus transfer.
Assembly code illustrating operation of the master transmitter mode is given at the end of the TWI section. Master Receiver Mode In the master receiver mode, a number of data bytes are received from a slave transmitter (see Figure 56). The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the TWINT flag is set by hardware. The software must then load TWDR with the 7-bit slave address and the data direction bit (SLA+R).
ATmega323(L) In ADC Noise Reduction Mode, Power-down mode, and Power-save mode, the clock system to the 2-wire Serial Interface is turned off. If the slave receive mode is enabled, the interface can still acknowledge a general call and its own slave address by using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the 2-wire Serial Interface will hold the SCL clock will low during the wake up and until the TWINT flag is cleared.
Table 37.
ATmega323(L) Figure 55.
ldi r16, 0xc8 out TWDR, r16 ldi r16, (1<
ATmega323(L) Table 38.
Figure 56.
ATmega323(L) in r16, TWSR ; Check value of TWI Status Register. If status cpi r16, MR_SLA_ACK ; different from MR_SLA_ACK, go to ERROR brne ERROR ldi r16, (1<
in r16, TWDR ; Input received data from TWDR. nop ; ldi r16, (1<
ATmega323(L) Figure 57. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
; ACK should be returned after receiving first ; data byte wait12:in r16,TWCR sbrs r16, TWINT ; Wait for TWINT flag set. This indicates that ; data has been received and ACK returned rjmp wait12 in r16, TWSR ; Check value of TWI Status Register. If status cpi r16, SR_DATA_ACK ; different from SR_DATA_ACK, go to ERROR brne ERROR in r16, TWDR nop ; Input received data from TWDR.
ATmega323(L) Table 40.
Figure 58. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A DATA $A8 Arbitration lost as master and addressed as slave A DATA $B8 A P or S $C0 A $B0 Last data byte transmitted.
ATmega323(L) ldi r16, 0x44 out TWDR, r16 ldi r16, (1<
.equ MT_DATA_NACK =$30 ;Data byte has been transmitted and NACK ;received .equ MT_ARB_LOST =$38 ;Arbitration lost in SLA+W or data bytes ;***** Master Receiver status codes ***** .equ MR_ARB_LOST =$38 ;Arbitration lost in SLA+R or NACK bit .equ MR_SLA_ACK =$40 ;SLA+R has been transmitted and ACK received .equ MR_SLA_NACK =$48 ;SLA+R has been transmitted and NACK received .equ MR_DATA_ACK =$50 ;Data byte has been received and ACK returned .
ATmega323(L) The Analog Comparator The analog comparator compares the input values on the positive pin PB2 (AIN0) and negative pin PB3 (AIN1). When the voltage on the positive pin PB2 (AIN0) is higher than the voltage on the negative pin PB3 (AIN1), the Analog Comparator Output, ACO, is set (one). The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
• Bit 4 - ACI: Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
ATmega323(L) Analog Comparator Multiplexed Input It is potor, as shown in Table . If ACME is cleared (zero) or ADEN is set (one), PB3 (AIN1) is applied to the negative input to the Analog Comparator. t Table 43. Analog Comparator Multiplexed Input ACME ADEN MUX2..
Analog to Digital Converter Features • • • • • • • • • • • • • 10-bit Resolution 0.5 LSB Integral Non-linearity ±2 LSB Absolute Accuracy 65 - 260 µs Conversion Time Up to 15 kSPS at Maximum Resolution Up to 76 kSPS at 8-bit Resolution Eight Multiplexed Single Ended Input Channels Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 2.
ATmega323(L) Figure 60. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ ADC[9:0] ADPS1 0 ADC DATA REGISTER (ADCH/ADCL) ADPS0 ADPS2 ADIF ADFR ADEN ADSC MUX1 15 ADC CTRL. & STATUS REGISTER (ADCSR) MUX0 MUX2 MUX4 MUX3 REFS0 ADLAR REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS PRESCALER CHANNEL SELECTION MUX DECODER AVCC CONVERSION LOGIC INTERNAL 2.56 V REFERENCE SAMPLE & HOLD COMPARATOR AREF 10-BIT DAC + AGND 1.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSR. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. A conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be set to zero by hardware when the conversion is completed.
ATmega323(L) keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. In certain situations, the ADC needs more clock cycles to initialization and minimize offset errors.
Figure 64. ADC Timing Diagram, Free Run Conversion One Conversion Cycle number 11 12 Next Conversion 13 1 2 3 4 ADC clock ADSC ADIF ADCH Sign and MSB of result ADCL LSB of result Sample & hold Conversion complete MUX and REFS update Table 44. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) Conversion Time (µs) Extended Conversion 13.5 25 125 - 500 Normal Conversions 1.
ATmega323(L) • Bit 7,6 - REFS1..0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 22. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). The user should disregard the first conversion result after changing these bits to obtain maximum accuracy. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. Table 45.
The ADC Control and Status Register – ADCSR Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 $06 ($26) ADCSR • Bit 7 - ADEN: ADC Enable Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
ATmega323(L) Table 47.
ADC Noise Canceling Techniques Digital circuitry inside and outside the ATmega323 generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. The analog part of the ATmega323 and all analog components in the application should have a separate analog ground plane on the PCB. This ground plane is connected to the digital ground plane via a single point on the PCB. 2.
ATmega323(L) ADC Characteristics – Preliminary Data(1) Symbol Min(2) Condition Resolution Single-ended Conversion Absolute accuracy VREF = 4V ADC clock = 200 kHz 1 Absolute accuracy VREF = 4V ADC clock = 1 MHz 4 LSB Absolute accuracy VREF = 4V ADC clock = 2 MHz 16 LSB Integral Non-linearity VREF > 2V 0.5 LSB Differential Non-linearity VREF > 2V 0.
I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Port A Port A is an 8-bit bi-directional I/O port with optional internal pull-ups.
ATmega323(L) PUD bit has to be set. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Table 48. DDAn Effects on Port A Pins DDAn PORTAn PUD (in SFIOR) I/O Pull Up 0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes PAn will source current if ext. pulled low. 0 1 1 Input No Tri-state (Hi-Z) 1 0 X Output No Push-pull Zero Output 1 1 X Output No Push-pull One Output Note: Port A Schematics Comment n: 7,6…0, pin number.
inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port B pins with alternate functions are shown in Table 49.: Table 49.
ATmega323(L) Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Table 50. DDBn Effects on Port B Pins DDBn PORTBn PUD (in SFIOR) I/O Pull-up 0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes PBn will Source Current if Ext. Pulled Low. 0 1 1 Input No Tri-state (Hi-Z) 1 0 X Output No Push-Pull Zero Output 1 1 X Output No Push-Pull One Output Note: Alternate Functions of Port B Comment n: 7,6…0, pin number.
OC0, Output compare match output: The PB3 pin can serve as an external output for the Timer/Counter0 compare match. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. See “8-bit Timers/Counters T/C0 and T/C2” on page 44 for further details, and how to enable the output. The OC0 pin is also the output pin for the PWM mode timer function. • AIN0/INT2 - Port B, Bit 2 AIN0, Analog Comparator Positive Input.
ATmega323(L) Figure 68. Port B Schematic Diagram (Pin PB1) PUD DDB1 PB1 PORTB1 TIMER1 CLOCK SOURCE MUX PUD: PULL-UP DISABLE CS12 CS11 CS10 Figure 69.
Figure 70. Port B Schematic Diagram (Pin PB3) PUD DDB3 PB3 PORTB3 PWRDN WP: WD: RL: RP: RD: PUD: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB PULL-UP DISABLE COM00 COM01 COMP. MATCH 0 PWM0 FOC0 AIN1 TO COMPARATOR Figure 71.
ATmega323(L) Figure 72. Port B Schematic Diagram (Pin PB5) RD MOS PULLUP PUD RESET Q R D DDB5 WD RESET R Q D PORTB5 PB5 DATA BUS C C RL WP RP WP: WD: RL: RP: RD: SPE: MSTR: PUD: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI ENABLE MASTER SELECT PULL-UP DISABLE MSTR SPE SPI MASTER OUT SPI SLAVE IN Figure 73.
Figure 74. Port B Schematic Diagram (Pin PB7) RD MOS PULLUP PUD RESET Q R D DDB7 C DATA BUS WD RESET R Q D PORTB7 PB7 C RL WP RP WP: WD: RL: RP: RD: SPE: MSTR PUD: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI ENABLE MASTER SELECT PULL-UP DISABLE MSTR SPE SPI ClLOCK OUT SPI CLOCK IN Port C Port C is an 8-bit bi-directional I/O port with optional internal pull-ups.
ATmega323(L) The Port C Data Register – PORTC Bit 7 6 5 4 3 2 1 0 PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 $15 ($35) The Port C Data Direction Register – DDRC Bit 7 6 5 4 3 2 1 0 DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 $14 ($34) The Port C Input Pins Address – PINC Bit 7 6
Alternate Functions of Port C • TOSC2 - Port C, Bit 7 TOSC2, Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PC7 is disconnected from the port, and becomes the inverting output of the oscillator amplifier. In this mode, a crystal oscillator is connected to this pin, and the pin can not be used as an I/O pin.
ATmega323(L) Port C Schematics Note that all port pins are synchronized. The synchronization latches are not shown in the figure. Figure 75.
Figure 76. Port C Schematic Diagram (Pins PC2 - PC5). The JTAG interface on these pins is not shown in the figure. RD MOS PULLUP PUD RESET Q R D DDCn C DATA BUS WD RESET R Q D PORTCn PCn C RL WP RP WP: WD: RL: RP: RD: PUD: n: WRITE PORTC WRITE DDRC READ PORTC LATCH READ PORTC PIN READ DDRC PULL-UP DISABLE 2..5 Figure 77.
ATmega323(L) Figure 78. Port C Schematic Diagram (Pins PC7) PUD 0 1 WP: WD: RL: RP: RD: AS2: PUD: Port D WRITE PORTC WRITE DDRC READ PORTC LATCH READ PORTC PIN READ DDRC ASYNCH SELECT T/C2 PULL-UP DISABLE Port D is an 8 bit bi-directional I/O port with optional internal pull-up resistors. Three I/O memory address locations are allocated for Port D, one each for the Data Register – PORTD, $12($32), Data Direction Register – DDRD, $11($31) and the Port D Input Pins – PIND, $10($30).
The Port D Data Register – PORTD Bit 7 6 5 4 3 2 1 0 PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 $12 ($32) The Port D Data Direction Register – DDRD Bit 7 6 5 4 3 2 1 0 DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 $11 ($31) The Port D Input Pins Address – PIND Bit 7 6 5 4 3 2
ATmega323(L) • ICP - Port D, Bit 6 ICP – Input Capture Pin: The PD6 pin can act as an input capture pin for Timer/Counter1. The pin has to be configured as an input (DDD6 cleared(zero)) to serve this function. See the timer description on how to enable this function. • OC1A - Port D, Bit 5 OC1A, Output compare matchA output: The PD5 pin can serve as an external output for the Timer/Counter1 output compareA. The pin has to be configured as an output (DDD5 set (one)) to serve this function.
Port D Schematics Note that all port pins are synchronized. The synchronization latches are not shown in the figures. Figure 79. Port D Schematic Diagram (Pin PD0) RD MOS PULLUP PUD RESET Q D DDD0 C DATA BUS WD RESET Q D PORTD0 C PD0 RL WP RP WP: WD: RL: RP: RD: RXD: RXEN: PUD: RXEN WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD UART RECEIVE DATA UART RECEIVE ENABLE PULL-UP DISABLE RXD Figure 80.
ATmega323(L) Figure 81. Port D Schematic Diagram (Pins PD2 and PD3) PUD WP: WD: RL: RP: RD: PUD: n: m: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD PULL-UP DISABLE 2, 3 0, 1 Figure 82.
Figure 83. Port D Schematic Diagram (Pin PD6) RD MOS PULLUP PUD RESET Q R D DDD6 WD RESET R Q D PORTD6 PD6 DATA BUS C C RL WP RP WP: WD: RL: RP: RD: ACIC: ACO: PUD: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD COMPARATOR IC ENABLE COMPARATOR OUTPUT PULL-UP DISABLE 0 NOISE CANCELER EDGE SELECT ICNC1 ICES1 ICF1 1 ACIC ACO Figure 84.
ATmega323(L) JTAG Interface and the On-chip Debug System Features: • JTAG (IEEE std. 1149.
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST - Test ReSeT - which is not provided. When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins, and the TAP controller is in reset. When programmed, the input TAP signals are internally pulled high and the JTAG is enabled for Boundary-Scan and programming. The device is shipped with this fuse programmed.
ATmega323(L) Figure 86. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 0 1 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR TAP Controller 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-Scan circuitry, JTAG programming circuitry, or On-Chip Debug system.
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the shift register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. • At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register - Shift-DR state.
ATmega323(L) mentation and JTAG instructions are therefore irrelevant for the user of the On-Chip Debug system. The JTAGEN fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN fuse must be programmed and no lock bits must be set for the OnChip debug system to work. The disabling of the On-Chip debug system when any lock bits are set is a security feature. Otherwise, the On-Chip debug system would have provided a back-door into a secured device.
A description of the programming specific JTAG instructions is given in “Programming specific JTAG instructions” on page 196. The details on programming through the JTAG interface is given in the section “Programming via the JTAG interface” on page 196 Bibliography 158 For more information about general Boundary-Scan, the following literature can be consulted: • IEEE: IEEE Std 1149.1-1990.
ATmega323(L) IEEE 1149.1 (JTAG) Boundary-scan Features • • • • • System Overview The Boundary-Scan chain has the capability of driving and observing the logic levels on the digital I/O pins. At system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long shift register. An external controller sets up the devices to drive values at their output pins, and observe the input values received from other devices.
Capture-DR controller state. The Bypass register can be used to shorten the scan chain on a system when the other devices are to be tested. Device Identification Register Figure 87 shows the structure of the Device Identification register. Figure 87. The format of the Device Identification register MSB Bit Device ID Version 31 LSB 28 27 12 11 1 0 Version Part Number Manufacturer ID 1 4 bits 16 bits 11 bits 1 bit Version is a 4 bit number identifying the revision of the component.
ATmega323(L) Figure 88. Reset Register To TDO From other internal and external reset sources From TDI D Q Internal reset ClockDR · AVR_RESET Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins. See “Boundary-scan Chain” on page 162 for a complete description. Boundary-scan Specific JTAG Instructions The instruction register is 4 bit wide, supporting up to 16 instructions.
SAMPLE_PRELOAD; $2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-Scan Chain is selected as Data Register. The active states are: AVR_RESET; $C • Capture-DR: Data on the external pins are sampled into the Boundary-Scan Chain. • Shift-DR: The Boundary-Scan Chain is shifted by the TCK input.
ATmega323(L) Figure 89. Boundary-scan Cell For bidirectional Port Pin with Pull-up Function. ShiftDR To Next Cell EXTEST Pullup Disable (PLD) Vcc 0 FF2 LD2 1 0 D Q D Q 1 G Output Control (OC) FF1 LD1 0 D Q D Q 0 1 1 G 0 1 FF0 LD0 0 D Q D 1 Q 0 1 Port Pin (PXn) Output Data (OD) G Input Data (ID) From Last Cell ClockDR UpdateDR The Boundary-Scan logic is not included in the figures in the Data Sheet.
Figure 90.
ATmega323(L) Figure 91. Observe-only Cell To next cell ShiftDR From system pin To system logic FF1 0 D Q 1 From previous cell Internal signals ClockDR ATmega323 contains a lot of scan chains for internal signals. The description of these signals are not public. However, the user must apply safe values to these cells before applying the Update-DR state of the TAP controller. Note: Incorrect setting of the scan cells for internal signals may cause signal contention and can damage the part.
Table 57.
ATmega323(L) ATmega323 Boundaryscan Order Table 64 shows the Scan order between TDI and TDO when the Boundary-Scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in the opposite bit order of the other ports.
Table 58. ATmega323 Boundary-scan Order (Continued) Bit Number Signal Name 104 SIG_PRIVATE27 103 SIG_PRIVATE28 102 SIG_PRIVATE29 101 SIG_PRIVATE30 100 SIG_PRIVATE31 99 SIG_PRIVATE32 98 SIG_PRIVATE33 97 SIG_PRIVATE34 96 SIG_PRIVATE35 95 SIG_PRIVATE36 94 SIG_PRIVATE37 93 SIG_PRIVATE38 92 SIG_PRIVATE39 91 SIG_PRIVATE40 90 SIG_PRIVATE41 89 SIG_PRIVATE42 88 PB0.Data 87 PB0.Control 86 PB0.PuLLup_Disable 85 PB1.Data 84 PB1.Control 83 PB1.PuLLup_Disable 82 PB2.
ATmega323(L) Table 58. ATmega323 Boundary-scan Order (Continued) Bit Number Signal Name 73 PB5.Data 72 PB5.Control 71 PB5.PuLLup_Disable 70 PB6.Data 69 PB6.Control 68 PB6.PuLLup_Disable 67 PB7.Data 66 PB7.Control 65 PB7.PuLLup_Disable 64 RSTT 63 SIG_PRIVATE43 62 SIG_PRIVATE44 61 SIG_PRIVATE45 60 SIG_PRIVATE46 59 PD0.Data 58 PD0.Control 57 PD0.PuLLup_Disable 56 PD1.Data 55 PD1.Control 54 PD1.PuLLup_Disable 53 PD2.Data 52 PD2.Control 51 PD2.
Table 58. ATmega323 Boundary-scan Order (Continued) Bit Number Signal Name 44 PD5.Data 43 PD5.Control 42 PD5.PuLLup_Disable 41 PD6.Data 40 PD6.Control 39 PD6.PuLLup_Disable 38 PD7.Data 37 PD7.Control 36 PD7.PuLLup_Disable 35 PC0.Data 34 PC0.Control 33 PC0.PuLLup_Disable 32 PC1.Data 31 PC1.Control 30 PC1.PuLLup_Disable 29 PC6.Data 28 PC6.Control 27 PC6.PuLLup_Disable 26 PC7.Data 25 PC7.Control 24 PC7.PuLLup_Disable 23 PA7.Data 22 PA7.Control 21 PA7.
ATmega323(L) Table 58. ATmega323 Boundary-scan Order (Continued) Bit Number Signal Name 11 PA3.Data 10 PA3.Control 9 PA3.PuLLup_Disable 8 PA2.Data 7 PA2.Control 6 PA2.PuLLup_Disable 5 PA1.Data 4 PA1.Control 3 PA1.PuLLup_Disable 2 PA0.Data 1 PA0.Control 0 PA0.PuLLup_Disable Module Port A Boundary-scan Description Language Files Boundary-Scan Description Language (BSDL) files describe Boundary-Scan capable devices in a standard format used by automated test-generation software.
Memory Programming Boot Loader Support The ATmega323 provides a mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates, controlled by the MCU using a Flash-resident Boot Loader program. This makes it possible to program the AVR in a target system without access to its SPI pins.
ATmega323(L) Figure 92.
Entering the Boot Loader The SPM instruction can access the entire Flash, but can only be executed from the Boot Loader Flash section. If no Boot Loader capability is needed, the entire Flash is Program available for application code. Entering the Boot Loader takes place by a jump or call from the application program. This may be initiated by some trigger such as a command received via USART or SPI interface, for example.
ATmega323(L) Perform a Page Write To execute page write, set up the address in the Z pointer, write “00101” to the five LSB in SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored. The page address must be written to Z14:Z7. During this operation, Z6:Z0 must be zero to ensure that the page is written correctly. It is recommended that the interrupts are disabled during the page write operation.
Table 61. Boot Lock Bit0 Protection Modes (Application Section) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 3 0 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
ATmega323(L) stant Addressing Using the LPM and SPM Instructions” on page 16 and in the Instruction set Manual. Bit 7 6 5 4 3 2 1 0 Rd - - BLB12 BLB11 BLB02 BLB01 LB2 LB1 The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock bits. To read the Fuse Low bits, load the Z pointer with $0000 and set the BLBSET and SPMEN bits in SPMCR.
Store Program Memory Control Register – SPMCR The Store Program Memory Control Register contains the control bits needed to control the programming of the Flash from internal code execution. Bit 7 6 5 4 3 2 1 0 $37 ($57) - ASB - ASRE BLBSET PGWRT PGERS SPMEN Read/Write R R R R/W R/W R/W R/W R/W Initial Value x 0 0 0 0 0 0 0 SPMCR • Bit 7 - Res: Reserved Bit This bit is a reserved bit in the ATmega323 and always reads as zero.
ATmega323(L) cycles. During page erase and page write, the SPMEN bit remains high until the operation is completed. Writing any other combination than “10001”, “01001”, “00101”, or “00001” in the lower five bits will have no effect. Preventing Flash Corruption During periods of low VCC, the Flash can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly.
sbiw loophi:looplo, 2 brne Wrloop ;use subi for PAGESIZEB<=256 ; execute page write subi ZL, low(PAGESIZEB) ;restore pointer sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256 ldi spmcrval, (1<
ATmega323(L) Program and Data Memory Lock Bits The ATmega323 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 63. The Lock bits can only be erased to “1” with the Chip Erase command. Table 63. Lock Bit Protection Modes Memory Lock Bits LB mode LB2 LB1 1 1 1 No memory lock features enabled for parallel, serial, and JTAG programming.
Fuse Bits The ATmega323 has 13 Fuse bits, divided in two groups. The Fuse High bits are OCDEN, JTAGEN, SPIEN, EESAVE, BOOTSZ1..0, and BOOTRST, and the Fuse Low bits are BODLEVEL, BODEN, and CKSEL3..0. All Fuses are accessible in parallel programming mode and when programming via the JTAG interface. In serial programming mode, all but the SPIEN Fuse is accessible. • When the OCDEN fuse is programmed, the On-chip debug system is enabled if the JTAGEN fuse is programmed.
ATmega323(L) Calibration Byte The ATmega323 has a one byte calibration value for the internal RC Oscillator. This byte resides in the high byte of address $000 in the signature address space. To make use of this byte, it should be read from this location and written into the normal Flash program memory by the external programmer. At start-up, the user software must read this Flash location and write the value to the OSCCAL register.
Table 64. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O PAGEL PD7 I Program Memory Page Load BS2 PA0 I Byte Select 2 (“0” Selects Low Byte, “1” Selects 2 nd High Byte) DATA PB7-0 I/O Bidirectional Data Bus (Output When OE is Low) Function Table 65.
ATmega323(L) 3. Set DATA to “1000 0000”. This is the command for Chip Erase. 4. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 5. Wait until RDY/BSY goes high before loading a new command. Programming the Flash The Flash is organized as 256 pages of 128 bytes each. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously.
H. Program Page 1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSYgoes low. 2. Wait until RDY/BSY goes high. (See Figure 95 for signal waveforms) I. End Page Programming 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. J. Repeat A through I 256 Times or Until All Data Has Been Programmed. Figure 94.
ATmega323(L) Programming the EEPROM The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” on page 185 for details on Command, Address and Data loading): 1. A: Load Command “0001 0001”. 2. H: Load Address High Byte ($00 - $03) 3. B: Load Address Low Byte ($00 - $FF) 4. C: Load Data Low Byte ($00 - $FF) K: Write Data Low Byte 1. Set BS1 to “0”. This selects low data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3.
5. Set BS to “1”. The Flash word high byte can now be read at DATA. 6. Set OE to “1”. Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash” on page 185 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. H: Load Address High Byte ($00 - $03) 3. B: Load Address ($00 - $FF) 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”.
ATmega323(L) The Lock bits can only be cleared by executing Chip Erase. Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 185 for details on Command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). Bit 7 = BODLEVEL Fuse bit Bit 6 = BODEN Fuse bit Bit 3..0 = CKSEL3..0 Fuse bits 3.
Parallel Programming Characteristics Figure 97. Parallel Programming Timing tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tRHBX tPHPL Write tWLWH WR tPLWL WLRL RDY/BSY tWLRH tXLOL tOHDZ tOLDV Read OE DATA Table 67. Parallel Programming Characteristics, TA = 25°C ± 10%, VCC = 5 V ± 10% Symbol Parameter Min VPP Programming Enable Voltage 11.
ATmega323(L) Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. Figure 98. Serial Programming and Verify ATmega323 2.7 - 5.
3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte ($53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all 4 bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a positive pulse and issue a new Programming Enable command. If the $53 is not seen within 32 attempts, there is no functional device connected. 4.
ATmega323(L) Programming Times for Nonvolatile Memory The internal RC oscillator is used to control programming time when programming or erasing Flash, EEPORM, fuses, and lock bits. During parallel or serial programming, the device is in reset, and this oscillator runs at its initial, uncalibrated frequency, which may vary from 0.5 MHz to 1.0 MHz. In software it is possible to calibrate this oscillator to 1.0 MHz (see “Calibrated Internal RC Oscillator” on page 40).
. Table 69. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. Read Program Memory 0010 H000 xxaa aaaa bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b.
ATmega323(L) Serial Programming Characteristics Figure 100. Serial Programming Timing MOSI tOVSH SCK tSHOX tSLSH tSHSL MISO tSLIV Table 70. Serial Programming Characteristics TA = -40°C to 85°C, VCC = 2.7V - 5.5V (Unless otherwise noted) Symbol Parameter 1/tCLCL Oscillator Frequency (VCC = 2.7 - 5.5 V) tCLCL 1/tCLCL Oscillator Period (VCC = 2.7 - 5.5 V) Oscillator Frequency (VCC = 4.0 - 5.5 V) tCLCL Oscillator Period (VCC = 4.0 - 5.
Programming via the JTAG interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low.
ATmega323(L) is not used to transfer data from the shift register. The data are automatically transferred to the Flash page buffer byte by byte in the Shift-DR state by an internal state machine. This is the only active state: • PROG_PAGEREAD ($7) The AVR specific public JTAG instruction to read one full Flash data page via the JTAG port. The 1032 bit Virtual Flash Page Read register is selected as data register.
Figure 101. Programming Enable Register TDI D A T A $A370 = D Q Programming enable ClockDR & PROG_ENABLE TDO Programming Command Register The Programming Command register is a 15 bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. The JTAG Programming Instruction Set is shown in Table 71. The state sequence when shifting in the programming commands is illustrated in Figure 102. Figure 102.
ATmega323(L) Table 71. JTAG Programming Instruction Set Instruction Notes TDI sequence TDO sequence 1a. Chip erase 0100011_10000000 0110001_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for chip erase complete 0110011_10000000 xxxxxox_xxxxxxxx 2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx 2b. Load Address High Byte 0000111_00aaaaaa xxxxxxx_xxxxxxxx 2c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 2d.
Table 71. JTAG Programming Instruction Set (Continued) Instruction Notes TDI sequence TDO sequence 6c. Write Fuse High byte 0110111_00000000 0110101_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6d. Poll for Fuse Write complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 6e. Load Data Low Byte 0010011_CB11A987 xxxxxxx_xxxxxxxx (3) 6f.
ATmega323(L) 4. Set bits to “0” to program the corresponding lock bit, “1” to leave the lock bit unchanged. 5. “0” = programmed, “1” = unprogrammed. 6.
Virtual Flash Page Load Register The Virtual Flash Page Load register is a virtual scan chain with length equal to the number of bits in one Flash page, 1024. Internally the shift register is 8 bit, and the data are automatically transferred to the Flash page buffer byte by byte. Shift in all instruction words in the page, starting with the LSB of the instruction with page address 0 and ending with the MSB of the instruction with page address 3F.
ATmega323(L) Virtual Flash Page Read Register The Virtual Flash Page Read register is a virtual scan chain with length equal to the number of bits in one Flash page plus 8, 1032 in total. Internally the shift register is 8 bit, and the data are automatically transferred from the Flash data page byte by byte. The first 8 cycles are used to transfer the first byte to the internal shift register, and the bits that are shifted out during these 8 cycles should be ignored.
Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start chip erase using programming instruction 1a. 3. Poll for chip erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 67 on page 190). Programming the Flash 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address using programming instructions 2b and 2c. 4. Load data using programming instructions 2d, 2e and 2f. 5.
ATmega323(L) 6. Enter JTAG instruction PROG_COMMANDS. 7. Repeat steps 3 to 6 until all data have been read. Programming the EEPROM 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM write using programming instruction 4a. 3. Load address using programming instructions 4b and 4c. 4. Load data using programming instructions 4d. 5. Write the data using programming instruction 4e. 6. Poll for EEPROM write complete using programming instruction 4f, or wait for tWLRH (refer to Table 67 on page 190). 7.
Reading the Signature Bytes 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Signature byte read using programming instruction 9a. 3. Load address $00 using programming instruction 9b. 4. Read first signature byte using programming instruction 9c. 5. Repeat steps 3 and 4 with address $01 and address $02 to read the second and third signature bytes, respectively. Reading the Calibration Byte 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Calibration byte read using programming instruction 10a. 3.
ATmega323(L) Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-1.0V to VCC+0.5V Voltage on RESET with respect to Ground......-1.0V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
DC Characteristics (Continued) TA = -40°C to 85°C, VCC = 2.7V to 5.5V (Unless Otherwise Noted) Symbol Parameter Condition Min Typ Active 4 MHz, VCC = 3V (ATmega323L) Active 8 MHz, VCC = 5V (ATmega323) Max Units 5 mA 15 mA 2.5 mA 8 mA Power Supply Current Idle 4 MHz, VCC = 3V ICC (ATmega323L) Idle 8 MHz, VCC = 5V (ATmega323) Power-down mode(5) WDT enabled, VCC = 3V 9 15.0 µA WDT disabled, VCC = 3V <1 4.
ATmega323(L) External Clock Drive Waveforms Figure 106. External Clock Drive Waveforms lH1 lL1 External Clock Drive Table 72. External Clock Drive VCC = 2.7V to 5.5V VCC = 4.0V to 5.5V Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Clock Period 250 125 ns tCHCX High Time 100 50 ns tCLCX Low Time 100 50 ns tCLCH Rise Time 1.6 0.5 µs tCHCL Fall Time 1.6 0.5 µs Min Max Min Max Units 0 4 0 8 MHz Table 73.
2-wire Serial Interface Characteristics Table 74 describes the requirements for devices connected to the 2-wire Serial Bus. The ATmega323 2-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 107. Table 74. 2-wire Serial Bus Requirements Symbol Parameter VIL VIH Units Input Low-voltage -0.5 0.3 VCC V Input High-voltage 0.7 VCC VCC + 0.5 V - V 0.4 V 250 ns 0 50(2) ns -10 10 µA - 10 pF 0 400 kHz fSCL ≤ 100 kHz 4.
ATmega323(L) cate at full speed (400 kHz) with other ATmega323 devices, as well as any other device with a proper tLOW acceptance margin. Figure 107.
ATmega323 Typical Characteristics – Preliminary Data The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
ATmega323(L) Figure 109. Active Supply Current vs. VCC ACTIVE SUPPLY CURRENT vs. Vcc FREQUENCY = 4 MHz 20 18 TA = 85˚C 16 TA = 25˚C 14 I cc(mA) 12 10 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 110. Active Supply Current vs. VCC, Device Clocked by Internal Oscillator ACTIVE SUPPLY CURRENT vs. Vcc DEVICE CLOCKED BY 1.0MHz INTERNAL RC OSCILLATOR 5 4.5 TA = 85˚C 4 TA = 25˚C 3.5 I cc(mA) 3 2.5 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
Figure 111. Active Supply Current vs. VCC, Device Clocked by External 32kHz Crystal ACTIVE SUPPLY CURRENT vs. Vcc DEVICE CLOCKED BY 32KHz CRYSTAL 1.4 TA = 25˚C 1.2 TA = 85˚C 1 I cc(mA) 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 112. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY TA= 25˚C 35 Vcc= 6V 30 Vcc= 5.5V I cc(mA) 25 20 Vcc= 5V Vcc= 4.5V 15 Vcc= 4V 10 Vcc= 3.6V Vcc= 3.3V Vcc= 3.0V Vcc= 2.
ATmega323(L) Figure 113. Idle Supply Current vs. VCC IDLE SUPPLY CURRENT vs. Vcc FREQUENCY = 4 MHz 12 10 TA = 85˚C TA = 25˚C I cc(mA) 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 114. Idle Supply Current vs. VCC, Device Clocked by Internal Oscillator IDLE SUPPLY CURRENT vs. Vcc DEVICE CLOCKED BY 1.0MHz INTERNAL RC OSCILLATOR 2.5 2 TA = 85˚C TA = 25˚C I cc(mA) 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
Figure 115. Idle Supply Current vs. VCC, Device Clocked by External 32kHz Crystal IDLE SUPPLY CURRENT vs. Vcc DEVICE CLOCKED BY 32KHz CRYSTAL 100 90 TA = 85˚C 80 TA = 25˚C 70 I cc(µA) 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 116. Power-down Supply Current vs. VCC POWER DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER DISABLED 8 TA = 85˚C 7 6 I cc(µA) 5 4 3 TA = 70˚C 2 1 TA = 45˚C TA = 25˚C 0 2.5 3 3.5 4 4.5 5 5.
ATmega323(L) Figure 117. Power-down Supply Current vs. VCC POWER DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER ENABLED 100 90 TA = 25˚C 80 70 TA = 85˚C I cc(µA) 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 118. Power-save Supply Current vs. VCC POWER SAVE SUPPLY CURRENT vs. Vcc WATCHDOG TIMER DISABLED 30 25 TA = 85˚C 20 I cc(µA) TA = 25˚C 15 10 5 0 2.5 3 3.5 4 4.5 5 5.
Figure 119. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. Vcc 0.9 0.8 0.7 TA = 25˚C 0.6 I cc(mA) TA = 85˚C 0.5 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Analog comparator offset voltage is measured as absolute offset Figure 120. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 5V 18 16 TA = 25˚C Offset Voltage (mV) 14 12 TA = 85˚C 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega323(L) Figure 121. Analog Comparator Offset voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. Vcc = 2.7V COMMON MODE VOLTAGE 10 TA = 25˚C Offset Voltage (mV) 8 6 TA = 85˚C 4 2 0 0 0.5 1 1.5 2 2.5 3 Common Mode Voltage (V) Figure 122. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT VCC = 6V TA = 25˚C 60 50 30 I ACLK (nA) 40 20 10 0 -10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.
Figure 123. Calibrated RC Oscillator Frequency vs. VCC CALIBRATED RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 1.02 TA = 25˚C TA = 45˚C TA = 70˚C 1 TA = 85˚C FRc (MHz) 0.98 0.96 0.94 0.92 0.9 0.88 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 124. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. Vcc 1600 TA = 25˚C 1400 TA = 85˚C F RC (KHz) 1200 1000 800 600 400 200 0 2 2.5 3 3.5 4 4.5 5 5.
ATmega323(L) Figure 125. Pull-Up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 120 TA = 25˚C 100 TA = 85˚C I OP (µA) 80 60 40 20 0 0 0.5 1 1.5 2 2.5 VOP (V) 3 3.5 4 4.5 5 Figure 126. Pull-Up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 30 TA = 25˚C 25 TA = 85˚C 15 I OP (µA) 20 10 5 0 0 0.5 1 1.5 2 2.
Figure 127. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 70 TA = 25˚C 60 TA = 85˚C 50 30 I OL (mA) 40 20 10 0 0 0.5 1 1.5 2 2.5 3 VOL (V) Figure 128. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 20 TA = 25˚C 18 16 TA = 85˚C 14 I OH (mA) 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega323(L) Figure 129. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 25 TA = 25˚C 20 TA = 85˚C 10 I OL (mA) 15 5 0 0 0.5 1 1.5 2 VOL (V) Figure 130. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 6 TA = 25˚C 5 TA = 85˚C 3 I OH (mA) 4 2 1 0 0 0.5 1 1.5 2 2.
Figure 131. I/O Pin Input Threshold Voltage vs. VCC I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc TA = 25˚C 2.5 Threshold Voltage (V) 2 1.5 1 0.5 0 2.7 4.0 5.0 Vcc Figure 132. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. Vcc TA = 25˚C 0.18 0.16 Input hysteresis (V) 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4.0 5.
ATmega323(L) Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $3F ($5F) SREG I T H S V N Z C 21 $3E ($5E) SPH - - - - SP11 SP10 SP9 SP8 22 $3D ($5D) SPL SP4 SP3 SP2 SP1 SP0 $3C ($5C) OCR0 $3B ($5B) GICR INT1 INT0 INT2 - - - IVSEL IVCE $3A ($5A) GIFR INTF1 INTF0 INTF2 - - - - - 34 $39 ($59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 35 $38 ($58) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $01 ($21) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 - - - 103 $00 ($20) TWBR Notes: 226 2-wire Serial Interface Bit Rate Register 101 1. When the OCDEN fuse is unprogrammed, the OSCCAL register is always accessed on this address. Refer to the debugger specific documentation for details on how to use the OCDR register. 2. Refer to the USART description for details on how to access UBRRH and UCSRC. 3.
ATmega323(L) Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 2 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 1 SBC Rd, Rr Subtract with Carry
Mnemonics Operands Description Operation Flags BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None #Clocks 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers 1 Rd, Rr Copy Register Word Rd ← Rr Rd+1:Rd ← Rr+1:Rr None MOVW None 1 1 LDI Rd, K Load Immediate Rd ← K None LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc.
ATmega323(L) Mnemonics Description Operation Flags CLH Operands Clear Half Carry Flag in SREG H←0 H #Clocks 1 NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr.
Ordering Information Speed (MHz) Power Supply 4 2.7-5.5V 8 4.0-5.5V Ordering Code Package Operation Range ATmega323L-4AC ATmega323L-4PC 44A 40P6 Commercial (0°C to 70°C) ATmega323L-4AI ATmega323L-4PI 44A 40P6 Industrial (-40°C to 85°C) ATmega323-8AC ATmega323-8PC 44A 40P6 Commercial (0°C to 70°C) ATmega323-8AI ATmega323-8PI 44A 40P6 Industrial (-40°C to 85°C) Package Type 44A 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 40P6 40-pin, 0.
ATmega323(L) Packaging Information 44A 44-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP), 10x10mm body, 2.0mm footprint, 0.8mm pitch. Dimension in Millimeters and (Inches)* JEDEC STANDARD MS-026 ACB 12.25(0.482) SQ 11.75(0.462) PIN 1 ID PIN 1 0.45(0.018) 0.30(0.012) 0.80(0.0315) BSC 10.10(0.394) SQ 9.90(0.386) 1.20(0.047) MAX 0.20(0.008) 0.09(0.004) 0˚~7˚ 0.75(0.030) 0.45(0.018) 0.15(0.006) 0.05(0.002) *Controlling dimension: millimetter REV.
40P6 40-lead, Plastic Dual Inline Parkage (PDIP), 0.600" wide Demension in Millimeters and (Inches)* JEDEC STANDARD MS-011 AC 52.71(2.075) 51.94(2.045) PIN 1 13.97(0.550) 13.46(0.530) 48.26(1.900) REF 4.83(0.190)MAX SEATING PLANE 0.38(0.015)MIN 3.56(0.140) 3.05(0.120) 2.54(0.100)BSC 1.65(0.065) 1.27(0.050) 0.56(0.022) 0.38(0.015) 15.88(0.625) 15.24(0.600) 0º ~ 15º REF 0.38(0.015) 0.20(0.008) 17.78(0.700)MAX *Controlling dimension: Inches REV.
Atmel Headquarters Atmel Product Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg.
