Datasheet

96
ATmega323(L)
1457E11/01
Bit 3 - USBS: Stop Bit Select
This bit selects number of stop bits to be inserted by the transmitter. The receiver
ignores this setting.
Bit 2:1 - UCSZ1:0: Character Size
The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits
(character size) in a frame the receiver and transmitter uses.
Bit 0 - UCPOL: Clock Polarity
This bit is used for synchronous mode only. Set this bit to zero when asynchronous
mode is used. The UCPOL bit sets the relationship between data output change and
data input sample, and the synchronous clock (XCK).
Table 33. Parity Mode
UPM1 UPM0 Parity Mode
00Disabled
0 1 (Reserved)
1 0 Enabled, Even Parity
1 1 Enabled, Odd Parity
Table 34. Stop Bit Select
USBS Stop Bit(s)
01-bit
12-bit
Table 35. Character Size
UCSZ2 UCSZ1 UCSZ0 Character Size
0005-bit
0016-bit
0107-bit
0118-bit
100Reserved
101Reserved
110Reserved
1119-bit
UCPOL
Transmitted Data Changed (Output
of TxD Pin)
Received Data Sampled (Input on
RxD Pin)
0 Falling XCK Edge Rising XCK Edge
1 Rising XCK Edge Falling XCK Edge