Datasheet
94
ATmega323(L)
1457E–11/01
• Bit 4 - FE: Frame Error
This bit is set if the next character in the receive buffer had a Frame Error when
received. I.e. when the first stop bit of the next character in the receive buffer is zero.
This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop
bit of received data is one. Always set this bit to zero when writing to UCSRA.
• Bit 3 - DOR: Data OverRun
This bit is set if a data overrun condition is detected. A data overrun occur when the
receive buffer is full (two characters), it is a new character waiting in the receive shift
register, and a new start bit is detected. Always set this bit to zero when writing to
UCSRA.
• Bit 2 - PE: Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received
and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the
receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA.
• Bit 1 - U2X: Double the USART Transmission Speed
Setting this bit only has effect for the asynchronous operation. Set this bit to zero when
using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8 effectively
doubling the transfer rate for asynchronous communication.
• Bit 0 - MPCM: Multi-processor Communication Mode
Setting this bit enables the Multi-processor Communication Mode. When the MPCM bit
is set, all the incoming frames received by the USART receiver that do not contain
address information will be ignored. The transmitter is unaffected by the MPCM setting.
For more detailed information see “Multi-processor Communication Mode” on page 89.
USART Control and Status
Register B – UCSRB
• Bit 7 - RXCIE: RX Complete Interrupt Enable
Setting this bit to one enables interrupt on the RXC flag. A USART Receive Complete
interrupt will be generated only if the RXCIE bit is set, the global interrupt flag in SREG
is set and the RXC bit in UCSRA is set.
• Bit 6 - TXCIE: TX Complete Interrupt Enable
Setting this bit to one enables interrupt on the TXC flag. A USART Transmit Complete
interrupt will be generated only if the TXCIE bit is set, the global interrupt flag in SREG is
set and the TXC bit in UCSRA is set.
• Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable
Setting this bit to one enables interrupt on the UDRE flag. A Data Register Empty inter-
rupt will be generated only if the UDRIE bit is set, the global interrupt flag in SREG is set
and the UDRE bit in UCSRA is set.
• Bit 4 - RXEN: Receiver Enable
Setting this bit to one enables the USART receiver. The receiver will override normal
port operation for the RxD pin when enabled. Disabling the receiver will flush the receive
buffer invalidating the FE, DOR and PE flags.
Bit 76543210
$0A ($2A)
RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 UCSRB
Read/Write R/W R/W R/W R/W R/W R/W R W
Initial Value00000000