Datasheet

72
ATmega323(L)
1457E11/01
Bit 0 - SPI2X: Double SPI Speed Bit
When this bit is set (one) the SPI speed (SCK Frequency) will be doubled when the SPI
is in master mode (see Table 27). This means that the minimum SCK period will be 2
CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to
work at f
ck
/4 or lower.
The SPI interface on the ATmega323 is also used for program memory and EEPROM
downloading or uploading. See page 191 for serial programming and verification.
The SPI Data Register SPDR
The SPI Data Register is a read/write register used for data transfer between the regis-
ter file and the SPI Shift register. Writing to the register initiates data transmission.
Reading the register causes the Shift Register Receive buffer to be read.
Bit 76543210
$0F ($2F)
MSB LSB SPDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial ValueXXXXXXXXUndefined