Datasheet

70
ATmega323(L)
1457E11/01
once the SS pin is driven high. If the SS pin is driven high during a transmission, the SPI
will stop sending and receiving immediately and both data received and data sent must
be considered as lost.
Data Modes There are four combinations of SCK phase and polarity with respect to serial data,
which are determined by control bits CPHA and CPOL. The SPI data transfer formats
are shown in Figure 43 and Figure 44.
Figure 43. SPI Transfer Format with CPHA = 0 and DORD = 0
Note: * Not defined but normally MSB of character just received.
Figure 44. SPI Transfer Format with CPHA = 1 and DORD = 0
Note: * Not defined but normally LSB of previously transmitted character.
SPI Control Register SPCR
Bit 7 - SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set
and the if the global interrupt enable bit in SREG is set.
Bit 6 - SPE: SPI Enable
When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI
operations.
Bit 5 - DORD: Data Order
When the DORD bit is set (one), the LSB of the data word is transmitted first.
When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
Bit 76543210
$0D ($2D)
SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000