Datasheet

59
ATmega323(L)
1457E11/01
Timer/Counter1 Input Capture
Register ICR1H and ICR1L
The input capture register is a 16-bit read-only register.
When the rising or falling edge (according to the input capture edge setting
ICES1) of
the signal at the input capture pin
ICP is detected, the current value of the
Timer/Counter1 Register
TCNT1 is transferred to the Input Capture Register ICR1.
At the same time, the input capture flag
ICF1 is set (one).
Since the Input Capture Register
ICR1 is a 16-bit register, a temporary register
TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously.
When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of
the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in
the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently,
the low byte ICR1L must be accessed first for a full 16-bit register read operation.
The TEMP register is also used when accessing TCNT1, OCR1A, and OCR1B. If the
main program and also interrupt routines accesses registers using TEMP, interrupts
must be disabled during access from the main program and interrupt routines.
Timer/Counter1 In PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register1A
OCR1A and the Output Compare Register1B OCR1B, form a dual 8, 9, or 10-bit,
free-running, glitch-free, and phase correct PWM with outputs on the PD5(OC1A) and
PD4(OC1B) pins. In this mode, the Timer/Counter1 acts as an up/down counter, count-
ing up from $0000 to TOP (see Table 21), where it turns and counts down again to zero
before the cycle is repeated. When the counter value matches the contents of the 8, 9,
or 10 least significant bits (depending on resolution) of OCR1A or OCR1B, the
PD5(OC1A)/PD4(OC1B) pins are set or cleared according to the settings of the
COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control Register
TCCR1A. Refer to Table 17 on page 55 for details.
Alternatively, the Timer/Counter1 can be configured to a PWM that operates at twice the
speed as in the mode described above. Then the Timer/Counter1 and the Output Com-
pare Register1A
OCR1A and the Output Compare Register1B OCR1B, form a dual
8, 9, or 10-bit, free-running and glitch-free PWM with outputs on the PD5(OC1A) and
PD4(OC1B) pins..
Bit 151413121110 9 8
$27 ($47)
MSB ICR1H
$26 ($46) LSB ICR1L
76543210
Read/WriteRRRRRRRR
RRRRRRRR
Initial Value00000000
00000000
Table 20. Timer TOP Values and PWM Frequency
CTC1 PWM11 PWM10 PWM Resolution Timer TOP Value Frequency
0 0 1 8-bit $00FF (255) f
TCK1
/510
0 1 0 9-bit $01FF (511) f
TCK1
/1022
0 1 1 10-bit $03FF(1023) f
TCK1
/2046
1 0 1 8-bit $00FF (255) f
TCK1
/256
1 1 0 9-bit $01FF (511) f
TCK1
/512
1 1 1 10-bit $03FF(1023) f
TCK1
/1024