Datasheet
58
ATmega323(L)
1457E–11/01
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read
and write access. If Timer/Counter1 is written to and a clock source is selected, the
Timer/Counter1 continues counting in the timer clock cycle after it is preset with the writ-
ten value.
Timer/Counter1 Output
Compare Register – OCR1AH
and OCR1AL
Timer/Counter1 Output
Compare Register – OCR1BH
and OCR1BL
The output compare registers are 16-bit read/write registers.
The Timer/Counter1 Output Compare Registers contain the data to be continuously
compared with Timer/Counter1. Actions on compare matches are specified in the
Timer/Counter1 Control and Status register. A software write to the Timer/Counter Reg-
ister blocks compare matches in the next Timer/Counter clock cycle. This prevents
immediate interrupts when initializing the Timer/Counter.
A compare match will set the compare interrupt flag in the CPU clock cycle following the
compare event.
Since the Output Compare Registers
– OCR1A and OCR1B – are 16-bit registers, a
temporary register TEMP is used when OCR1A/B are written to ensure that both bytes
are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH,
the data is temporarily stored in the TEMP register. When the CPU writes the low byte,
OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or
OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a
full 16-bit register write operation.
The TEMP register is also used when accessing TCNT1 and ICR1. If the main program
and also interrupt routines perform access to registers using TEMP, interrupts must be
disabled during access from the main program and interrupt routines.
Bit 151413121110 9 8
$2B ($4B)
MSB OCR1AH
$2A ($4A) LSB OCR1AL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
00000000
Bit 151413121110 9 8
$29 ($49)
MSB OCR1BH
$28 ($48) LSB OCR1BL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
00000000