Datasheet
51
ATmega323(L)
1457E–11/01
Note: n = 0 or 2
In overflow PWM mode, the table above is only valid for OCRn = $FF.
In up/down PWM mode, the Timer Overflow Flag, TOV0 or TOV2, is set when the
counter advances from $00. In overflow PWM mode, the Timer Overflow Flag is set as
in normal Timer/Counter mode. Timer Overflow Interrupt0 and 2 operate exactly as in
normal Timer/Counter mode, i.e. they are executed when TOV0 or TOV2 are set pro-
vided that Timer Overflow Interrupt and global interrupts are enabled. This does also
apply to the Timer Output Compare flag and interrupt.
Asynchronous Status
Register – ASSR
• Bit 7..4 - Res: Reserved Bits
These bits are reserved bits in the ATmega323 and always read as zero.
• Bit 3 - AS2: Asynchronous Timer/Counter2
When AS2 is cleared (zero), Timer/Counter2 is clocked from the internal system clock,
CK. When AS2 is set (one), Timer/Counter2 is clocked from the TOSC1 pin. Pins PC6
and PC7 are connected to a crystal oscillator and cannot be used as general I/O pins.
When the value of this bit is changed, the contents of TCNT2, OCR2, and TCCR2 might
be corrupted.
• Bit 2 - TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes
set (one). When TCNT2 has been updated from the temporary storage register, this bit
is cleared (zero) by hardware. A logical zero in this bit indicates that TCNT2 is ready to
be updated with a new value.
• Bit 1 - OCR2UB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes
set (one). When OCR2 has been updated from the temporary storage register, this bit is
cleared (zero) by hardware. A logical zero in this bit indicates that OCR2 is ready to be
updated with a new value.
• Bit 0 - TCR2UB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes
set (one). When TCCR2 has been updated from the temporary storage register, this bit
is cleared (zero) by hardware. A logical zero in this bit indicates that TCCR2 is ready to
be updated with a new value.
Table 16. PWM Outputs OCRn = $00 or $FF
COMn1 COMn0 OCRn Output PWMn
10$00 L
10$FF H
11$00 H
11$FF L
Bit 76543 2 1 0
$22 ($22) ----AS2TCN2UBOCR2UBTCR2UBASSR
Read/Write R R R R R/W R R R
Initial Value00000 0 0 0