Datasheet
37
ATmega323(L)
1457E–11/01
is enabled and is configured as level triggered (only INT0/INT1), the interrupt will trigger
as long as the pin is held low.
MCU Control Register –
MCUCR
The MCU Control Register contains control bits for general MCU functions.
• Bit 7- SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the pro-
grammers purpose, it is recommended to set the Sleep Enable (SE) bit just before the
execution of the SLEEP instruction.
• Bits 6..4 - SM2..0: Sleep Mode Select Bits 2, 1 and 0
These bits select between the six available sleep modes as shown in Table 8.
Note: 1. Standby Mode and Extended Standby Mode are only available with external crystals
or resonators.
• Bits 3, 2 - ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the
corresponding interrupt mask in the GICR are set. The level and edges on the external
INT1 pin that activate the interrupt are defined in Table 9. The value on the INT1 pin is
sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last
longer than one clock period will generate an interrupt. Shorter pulses are not guaran-
teed to generate an interrupt. If low level interrupt is selected, the low level must be held
until the completion of the currently executing instruction to generate an interrupt.
Bit 76543210
$37 ($57)
SE SM2 SM1 SM0 ISC11 ISC10 ISC01 ISC00 MCUCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Table 8. Sleep Mode Select
SM2 SM1 SM0 Sleep Mode
000Idle
0 0 1 ADC Noise Reduction
010Power-down
011Power-save
100Reserved
101Reserved
110Standby
(1)
1 1 1 Extended Standby
(1)
Table 9. Interrupt 1 Sense Control
ISC11 ISC10 Description
0 0 The low level of INT1 generates an interrupt request.
0 1 Any logical change on INT1 generates an interrupt request.
1 0 The falling edge of INT1 generates an interrupt request.
1 1 The rising edge of INT1 generates an interrupt request.