Datasheet

34
ATmega323(L)
1457E11/01
The General Interrupt Flag
Register GIFR
Bit 7 - INTF1: External Interrupt Flag1
When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one).
If the I-bit in SREG and the INT1 bit in GICR are set (one), the MCU will jump to the cor-
responding interrupt vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always
cleared when INT1 is configured as a level interrupt.
Bit 6 - INTF0: External Interrupt Flag0
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one).
If the I-bit in SREG and the INT0 bit in GICR are set (one), the MCU will jump to the cor-
responding interrupt vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always
cleared when INT0 is configured as a level interrupt.
Bit 5 - INTF2: External Interrupt Flag2
When an event on the INT2 pin triggers an interrupt request, INTF2 becomes set (one).
If the I-bit in SREG and the INT2 bit in GICR are set (one), the MCU will jump to the cor-
responding interrupt vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
Bits 4..0 - Res: Reserved Bits
These bits are reserved bits in the ATmega323 and always read as zero.
The Timer/Counter Interrupt
Mask Register TIMSK
Bit 7 - OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is
executed if a compare match in Timer/Counter2 occurs, i.e. when the OCF2 bit is set in
the Timer/Counter Interrupt Flag Register
TIFR.
Bit 6 - TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if
an overflow in Timer/Counter2 occurs, i.e. when the TOV2 bit is set in the Timer/Counter
Interrupt Flag Register
TIFR.
Bit 5 - TICIE1: Timer/Counter1 Input Capture Interrupt Enable
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt is
executed if a capture triggering event occurs on PD6 (ICP), i.e., when the ICF1 bit is set
in the Timer/Counter Interrupt Flag Register
TIFR.
Bit 76543210
$3A ($5A)
INTF1INTF0INTF2-----GIFR
Read/WriteR/WR/WR/WRRRRR
Initial Value00000000
Bit 76543210
$39 ($59)
OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 TIMSK
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000