Datasheet

ATmega323(L)

1457E–11/01

corresponding interrupt of External Interrupt Request 1 is executed from the INT1 inter-

rupt vector. See also “External Interrupts” on page 36.

• Bit 6 - INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is activated. The Interrupt Sense Control0 bits 1/0 (ISC01 and

ISC00) in the MCU general Control Register (MCUCR) define whether the external

interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on

the pin will cause an interrupt request even if INT0 is configured as an output. The corre-

sponding interrupt of External Interrupt Request 0 is executed from the INT0 interrupt

vector. See also “External Interrupts” on page 36.

• Bit 5 - INT2: External Interrupt Request 2 Enable

When the INT2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is activated. The Interrupt Sense Control2 bit (ISC02) in the

MCU Control and Status Register (MCUCSR) defines whether the external interrupt is

activated on rising or falling edge of the INT2 pin. Activity on the pin will cause an inter-

rupt request even if INT2 is configured as an output. The corresponding interrupt of

External Interrupt Request 2 is executed from the INT2 interrupt vector. See also “Exter-

nal Interrupts” on page 36.

• Bits 4..2 - Res: Reserved bits

These bits are reserved bits in the ATmega323 and always read as zero.

• Bit 1 - IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the

Flash memory. When this bit is set (one), the interrupt vectors are moved to the begin-

ning of the Boot Loader section of the Flash. The actual address to the start of the boot

Flash section is determined by the BOOTSZ fuses. Refer to the section “Boot Loader

Support” on page 172 for details. To avoid unintentional changes of interrupt vector

tables, a special write procedure must be followed to change the IVSEL bit:

1. Set the Interrupt Vector Change Enable (IVCE) bit.

2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will be automatically disabled while this sequence is executed. Interrupts are

disabled in the cycle IVCE is set, and they remain disabled until after the instruction fol-

lowing the write to IVSEL. If IVSEL is not written, interrupts remain disabled in four

cycles. The I-flag in the Status Register is unaffected by the automatic disabling.

Note: If Boot Lock bits BLB02 or BLB12 are set, changing the interrupt vector table will

change from what part of the program memory interrupts are allowed. Refer to the sec-

tion “Boot Loader Support” on page 172 for details on Boot Lock bits.

• Bit 0 - IVCE: Interrupt Vector Change Enable

The IVCE bit must be set to enable change of the IVSEL bit. IVCE is cleared by hard-

ware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will

disable interrupts, as explained in the IVSEL description above.