Datasheet
32
ATmega323(L)
1457E–11/01
power-down mode, the user can avoid the three conditions above to ensure that the ref-
erence is turned off before entering power-down mode.
Interrupt Handling The ATmega323 has two 8-bit Interrupt Mask control registers: GICR
– General Inter-
rupt Control register and TIMSK
– Timer/Counter Interrupt Mask register.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-
rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction
– RETI – is executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logic one to the flag
bit position(s) to be cleared.
If an interrupt condition occurs while the corresponding interrupt enable bit is cleared
(zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software.
If one or more interrupt conditions occur while the global interrupt enable bit is cleared
(zero), the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for
as long as the interrupt condition is present.
Note that the status register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles
minimum. After 4 clock cycles the program vector address for the actual interrupt han-
dling routine is executed. During this 4 clock cycle period, the Program Counter (14 bits)
is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this
jump takes 3 clock cycles. If an interrupt occurs during execution of a multi-cycle instruc-
tion, this instruction is completed before the interrupt is served. If an interrupt occurs
when the MCU is in sleep mode, the interrupt execution response time is increased by 4
clock cycles.
A return from an interrupt handling routine takes 4 clock cycles. During these 4 clock
cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer
is incremented by 2, and the I flag in SREG is set. When AVR exits from an interrupt, it
will always return to the main program and execute one more instruction before any
pending interrupt is served.
The General Interrupt Control
Register – GICR
l
• Bit 7 - INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is activated. The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity
on the pin will cause an interrupt request even if INT1 is configured as an output. The
Bit 76543210
$3B ($5B)
INT1 INT0 INT2 - - - IVSEL IVCE GICR
Read/Write R/W R/W R/W R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0