Datasheet
31
ATmega323(L)
1457E–11/01
(zero), a falling edge on INT2 activates the interrupt. If ISC2 is set (one) a rising edge on
INT2 activates the interrupt. Edges on INT2 are registered asynchronously. Pulses on
INT2 wider than 50 ns will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt. When changing the ISC2 bit, an interrupt can occur. Therefore, it
is recommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR reg-
ister. Then, the ISC2 bit can be changed. Finally, the INT2 interrupt flag should be
cleared by writing a logical one to its Interrupt Flag bit in the GIFR register before the
interrupt is re-enabled.
• Bit 5 - Res: Reserved Bit
This bit is a reserved bit in the ATmega323 and always reads as zero.
• Bit 4 - JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register
selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or
by writing a logic zero to the flag.
• Bit 3 - WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 2 - BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 1 - EXTRF: External Reset Flag
This bit is set if an external reset occurs. The bit is reset by a Power-on Reset, or by writ-
ing a logic zero to the flag.
• Bit 0 - PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to
the flag.
To make use of the reset flags to identify a reset condition, the user should read and
then reset the MCUCSR as early as possible in the program. If the register is cleared
before another reset occurs, the source of the reset can be found by examining the reset
flags.
Internal Voltage Reference ATmega323 features an internal bandgap reference with a nominal voltage of 1.22V.
This reference is used for Brown-out Detection, and it can be used as an input to the
Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the
internal bandgap reference.
Voltage Reference Enable
Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used.
The maximum start-up time is TBD. To save power, the reference is not always turned
on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODEN fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting
the ACBG bit in ACSR).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit, the user must always
allow the reference to start up before the output from the Analog Comparator is used.
The bandgap reference uses typically 10 µA, and to reduce power consumption in