Datasheet

30
ATmega323(L)
1457E11/01
Figure 28. Brown-out Reset During Operation
The hysteresis on V
BOT
: V
BOT+
= V
BOT
+ 25 mV, V
BOT-
= V
BOT
- 25 mV
Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle dura-
tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period
t
TOUT
. Refer to page 63 for details on operation of the Watchdog Timer.
Figure 29. Watchdog Reset During Operation
MCU Control and Status
Register MCUCSR
The MCU Control and Status Register contains control bits for general MCU functions,
and provides information on which reset source caused an MCU Reset.
Bits 7 - JTD: JTAG interface disable
When this bit is cleared (zero), the JTAG interface is enabled if the JTAGEN fuse is pro-
grammed. If this bit is set (one), the JTAG interface is disabled. To avoid unintentional
disabling of the JTAG interface, the user software must write this bit as one twice within
four cycles to set the bit.
Bit 6 - ISC2: Interrupt Sense Control 2
The asynchronous external interrupt 2 is activated by the external pin INT2 if the SREG
I-flag and the corresponding interrupt mask in the GICR are set. If ISC2 is cleared
V
CC
RESET
TIME-OUT
INTERNAL
RESET
V
BOT-
V
BOT+
t
TOUT
CK
Bit 76543210
$34 ($54)
JTD ISC2 - JTRF WDRF BORF EXTRF PORF MCUCSR
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 See Bit Description