Datasheet

22
ATmega323(L)
1457E11/01
The Stack Pointer SP The ATmega323 Stack Pointer is implemented as two 8-bit registers in the I/O space
locations $3E ($5E) and $3D ($5D). As the ATmega323 data memory has $860 loca-
tions, 12 bits are used.
The Stack Pointer points to the data SRAM stack area where the Subroutine and Inter-
rupt Stacks are located. This Stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above $60. The Stack Pointer is decremented by one when
data is pushed onto the Stack with the PUSH instruction, and it is decremented by two
when the return address is pushed onto the Stack with subroutine call and interrupt. The
Stack Pointer is incremented by one when data is popped from the Stack with the POP
instruction, and it is incremented by two when data is popped from the Stack with return
from subroutine RET or return from interrupt RETI.
Reset and Interrupt
Handling
The ATmega323 provides nineteen different interrupt sources. These interrupts and the
separate reset vector, each have a separate program vector in the program memory
space. All interrupts are assigned individual enable bits which must be set (one)
together with the I-bit in the Status Register in order to enable the interrupt. Depending
on the program counter value, interrupts may be disabled when Boot Lock bits BLB02 or
BLB12 are set. See the section Boot Loader Support on page 172 for details
The lowest addresses in the program memory space are automatically defined as the
Reset and Interrupt vectors. The complete list of vectors is shown in Table 3. The list
also determines the priority levels of the different interrupts. The lower the address the
higher is the priority level. RESET has the highest priority, and next is INT0
the Exter-
nal Interrupt Request 0, etc. The interrupt vectors can be moved to the start of the boot
Flash section by setting the IVSEL bit in the General Interrupt Control Register (GICR).
See the GICR description on page 32 for details..
Bit 151413121110 9 8
$3E ($5E)
----SP11SP10SP9SP8SPH
$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/WriteRRRRR/WR/WR/WR/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
00000000
Table 3. Reset and Interrupt Vectors
Vector No. Program Address
(2)
Source Interrupt Definition
1 $000
(1)
RESET
External Pin, Power-on Reset,
Brown-out Reset and Watchdog
Reset
2 $002 INT0 External Interrupt Request 0
3 $004 INT1 External Interrupt Request 1
4 $006 INT2 External Interrupt Request 2
5 $008 TIMER2 COMP Timer/Counter2 Compare Match
6 $00A TIMER2 OVF Timer/Counter2 Overflow
7 $00C TIMER1 CAPT Timer/Counter1 Capture Event
8 $00E TIMER1 COMPA Timer/Counter1 Compare Match A
9 $010 TIMER1 COMPB Timer/Counter1 Compare Match B