Datasheet
20
ATmega323(L)
1457E–11/01
Notes: 1. When the OCDEN fuse is unprogrammed, the OSCCAL register is always accessed
on this address. Refer to the debugger specific documentation for details on how to
use the OCDR register.
2. Refer to the USART description for details on how to access UBRRH and UCSRC.
All ATmega323 I/Os and peripherals are placed in the I/O space. The I/O locations are
accessed by the IN and OUT instructions, transferring data between the 32 general-pur-
pose working registers and the I/O space. I/O registers within the address range $00 -
$1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to
the instruction set chapter for more details. When using the I/O specific commands IN
and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as
SRAM, $20 must be added to these addresses. All I/O register addresses throughout
this document are shown with the SRAM address in parentheses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O register, writing a one back into any
$15 ($35) PORTC Data Register, Port C
$14 ($34) DDRC Data Direction Register, Port C
$13 ($33) PINC Input Pins, Port C
$12 ($32) PORTD Data Register, Port D
$11 ($31) DDRD Data Direction Register, Port D
$10 ($30) PIND Input Pins, Port D
$0F ($2F) SPDR SPI I/O Data Register
$0E ($2E) SPSR SPI Status Register
$0D ($2D) SPCR SPI Control Register
$0C ($2C) UDR USART I/O Data Register
$0B ($2B) UCSRA USART Control and Status Register A
$0A ($2A) UCSRB USART Control and Status Register B
$09 ($29) UBRRL USART Baud Rate Register Low Byte
$08 ($28) ACSR Analog Comparator Control and Status Register
$07 ($27) ADMUX ADC Multiplexer Select Register
$06 ($26) ADCSR ADC Control and Status Register
$05 ($25) ADCH ADC Data Register High
$04 ($24) ADCL ADC Data Register Low
$03 ($23) TWDR 2-wire Serial Interface Data Register
$02 ($22) TWAR 2-wire Serial Interface (Slave) Address Register
$01 ($21) TWSR 2-wire Serial Interface Status Register
$00 ($20) TWBR 2-wire Serial Interface Bit Rate Register
Table 2. ATmega323 I/O Space (Continued)
I/O Address (SRAM
Address) Name Function