Datasheet

196
ATmega323(L)
1457E–11/01
Programming via the
JTAG interface
Programming through the JTAG interface requires control of the four JTAG specific
pins: TCK, TMS, TDI and TDO. Control of the reset and clock pins is not required.
To be able to use the JTAG interface, the JTAGEN fuse must be programmed. The
device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR
must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low.
Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are available
for programming. This provides a means of using the JTAG pins as normal port pins in
running mode while still allowing In-System Programming via the JTAG interface. Note
that this technique can not be used when using the JTAG pins for Boundary-Scan or
On-chip Debug. In these cases the JTAG pins must be dedicated for this purpose.
As a definition in this data sheet, the LSB is shifted in and out first of all shift registers.
Programming specific
JTAG instructions
The instruction register is 4 bit wide, supporting up to 16 instructions. The JTAG instruc-
tions useful for Programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format.
The text describes which data register is selected as path between TDI and TDO for
each instruction.
The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can
also be used as an idle state between JTAG sequences.
AVR_RESET ($C) The AVR specific public JTAG instruction for setting the AVR device in the Reset Mode
or taking the device out from the Reset Mode. The TAP controller is not reset by this
instruction. The one bit Reset Register is selected as Data Register. Note that the reset
will be active as long as there is a logic 'one' in the Reset Chain. The output from this
chain is not latched.
The active states are:
• Shift-DR: The Reset Register is shifted by the TCK input.
PROG_ENABLE ($4) The AVR specific public JTAG instruction for enabling programming via the JTAG port.
The 16 bit Programming Enable register is selected as data register. The active states
are the following:
• Shift-DR: the programming enable signature is shifted into the data register.
• Update-DR: the programming enable signature is compared to the correct value,
and programming mode is entered if the signature is valid.
PROG_COMMANDS ($5) The AVR specific public JTAG instruction for entering programming commands via the
JTAG port. The 15 bit Programming Command register is selected as data register. The
active states are the following:
• Capture-DR: the result of the previous command is loaded into the data register.
• Shift-DR: the data register is shifted by the TCK input, shifting out the result of the
previous command and shifting in the new command.
• Update-DR: the programming command is applied to the Flash inputs
• Run-Test/Idle: one clock cycle is generated, executing the applied command (not
always required, see Table 71 below).
PROG_PAGELOAD ($6) The AVR specific public JTAG instruction to directly load the Flash data page via the
JTAG port. The 1024 bit Virtual Flash Page Load register is selected as data register.
This is a virtual scan chain with length equal to the number of bits in one Flash page.
Internally the shift register is 8 bit. Unlike most JTAG instructions, the Update-DR state