Datasheet

178
ATmega323(L)
1457E–11/01
Store Program Memory
Control Register – SPMCR
The Store Program Memory Control Register contains the control bits needed to control
the programming of the Flash from internal code execution.
• Bit 7 - Res: Reserved Bit
This bit is a reserved bit in the ATmega323 and always reads as zero. This bit should be
written to zero when writing SPMCR.
• Bit 6 - ASB: Application Section Busy
Before entering the application section after a boot loader operation (page erase or
page write) the user software must verify that this bit is cleared. In future devices, this bit
will be set to “1” by page erase and page write. In ATmega323, this bit always reads as
zero.
• Bit 5 - Res: Reserved Bit
This bit is a reserved bit in the ATmega323 and always reads as zero. This bit should be
written to zero when writing SPMCR.
• Bit 4 - ASRE: Application Section Read Enable
Before re-entering the application section, the user software must set this bit together
with the SPMEN bit and execute SPM within 4 clock cycles.
• Bit 3 - BLBSET: Boot Lock Bit Set
If this bit is set at the same time as SPMEN, the next SPM instruction within four clock
cycles will set Boot Lock Bits. Alternatively, an LPM instruction within five cycles will
read either the Lock Bits or the Fuse Bits. The BLBSET bit will auto-clear upon comple-
tion of the SPM or LPM instruction, or if no SPM, or LPM, instruction is executed within
four, respectively five, clock cycles.
• Bit 2 - PGWRT: Page Write
If this bit is set at the same time as SPMEN, the next SPM instruction within four clock
cycles executes page write, with the data stored in the temporary buffer. The page
address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored.
The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction
is executed within four clock cycles. The CPU is halted during the entire page write
operation.
• Bit 1 - PGERS: Page Erase
If this bit is set at the same time as SPMEN, the next SPM instruction within four clock
cycles executes page erase. The page address is taken from the high part of the Z
pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon comple-
tion of a page erase, or if no SPM instruction is executed within four clock cycles. The
CPU is halted during the entire page erase operation.
• Bit 0 - SPMEN: Store Program Memory Enable
This bit enables the SPM instruction for the next four clock cycles. If set together with
either ASRE, BLBSET, PGWRT or PGERS, the following SPM instruction will have a
special meaning, see description above. If only SPMEN is set, the following SPM
instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z
pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon com-
pletion of an SPM instruction, or if no SPM instruction is executed within four clock
Bit 76543210
$37 ($57)
- ASB - ASRE BLBSET PGWRT PGERS SPMEN SPMCR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value x 0 0 0 0 0 0 0