Datasheet

164
ATmega323(L)
1457E11/01
Figure 90. General Port Pin Schematic diagram
When no alternate port function is present, the Input Data - ID corresponds to the PINn
register value, Output Data corresponds to the PORTn register, Output Control corre-
sponds to the Data Direction - DDn register, and the PuLL-up Disable - PLD -
corresponds to logic expression (DDn OR NOT(PORTBn)).
Digital alternate port functions are connected outside the dotted box in Figure 90 to
make the scan chain read the actual pin value. For Analog function, there is a direct
connection from the external pin to the analog circuit, and a scan chain is inserted on
the interface between the digital logic and the analog circuit.
Scanning RESET The RESET pin accepts 5V active low logic for standard reset operation. An observe-
only cell as shown in Figure 91 is inserted at the output from the reset detector; RST.
Note: The scanned signal is active high, i.e., the RST signal is the inverse of the external
RESET pin.
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PXn
WP:
WD:
RL:
RP:
RD:
n:
WRITE PORTX
WRITE DDRX
READ PORTX LATCH
READ PORTX PIN
READ DDRX
0-7
DDXn
PORTXn
RL
RP
PUD
PUD: PULL-UP DISABLE
PLD
OD
OC
ID
See Boundary Scan
description for details
PuD: JTAG PULL-UP DISABLE
OC: JTAG OUTPUT CONTROL
OD: JTAG OUTPUT DATA
ID: JTAG INPUT DATA