Datasheet

162
ATmega323(L)
1457E–11/01
SAMPLE_PRELOAD; $2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of
the input/output pins without affecting the system operation. However, the output latches
are not connected to the pins. The Boundary-Scan Chain is selected as Data Register.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-Scan Chain.
• Shift-DR: The Boundary-Scan Chain is shifted by the TCK input.
• Update-DR: Data from the Boundary-Scan chain is applied to the output latches.
However, the output latches are not connected to the pins.
AVR_RESET; $C The AVR specific public JTAG instruction for forcing the AVR device into the Reset
Mode or releasing the JTAG reset source. The TAP controller is not reset by this instruc-
tion. The one bit Reset Register is selected as Data Register. Note that the reset will be
active as long as there is a logic 'one' in the Reset Chain. The output from this chain is
not latched.
The active states are:
• Shift-DR: The Reset Register is shifted by the TCK input.
BYPASS; $F Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
• Capture-DR: Loads a logic ‘0’ into the Bypass Register.
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
Boundary-scan Chain The Boundary-Scan chain has the capability of driving and observing the logic levels on
the digital I/O pins.
Note: Compatibility issues regarding future devices: Future devices, included replacements for
ATmega323 will have Pull-Up Enable signals instead of the Pull-Up Disable signals in the
scan path (i.e. inverted logic). The scan cell for the reset signal will have the same logic
level as the external pin (i.e. inverted logic). The length of the scan-chain is likely to
change in future devices.
Scanning the Digital Port Pins Figure 89 shows the Boundary-Scan Cell for Bidirectional Port Pins with Pull-up func-
tion. The cell consists of a standard Boundary-Scan cell for the Pull-up function, and a
Bidirectional pin cell that combines the three signals Output Control - OC, Output Data -
OD, and Input Data - ID, into only a two-stage shift register.