Datasheet

155
ATmega323(L)
1457E11/01
Figure 86. TAP Controller State Diagram
TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of the
Boundary-Scan circuitry, JTAG programming circuitry, or On-Chip Debug system. The
state transitions depicted in Figure 86 depends on the signal present on TMS (shown
adjacent to each state transition) at the time of the rising edge at TCK. The initial state
after a Power-On Reset is Test-Logic-Reset.
As a definition in this document, the LSB is shifted in and out first for all shift registers.
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG inter-
face is
At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter
the Shift Instruction Register - Shift-IR state. While TMS is low, shift the 4 bit JTAG
instructions into the JTAG instruction register from the TDI input at the rising edge of
TCK, while the captured IR-state 0x01 is shifts out on the TDO pin. The JTAG
Instruction selects a particular Data Register as path between TDI and TDO and
controls the circuitry surrounding the selected Data Register.
Test-Logic-Reset
Run-Test/Idle
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
Select-DR Scan
Capture-DR
0
1
0
11 1
00
00
11
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
00
11